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Conferences in DBLP

VLSI Design (vlsid)
2008 (conf/vlsid/2008)

  1. Gateway to Chips: High Speed I/O Signalling and Interface. [Citation Graph (, )][DBLP]

  2. DFM / DFT / SiliconDebug / Diagnosis. [Citation Graph (, )][DBLP]

  3. Oversampling Analog-to-Digital Converter Design. [Citation Graph (, )][DBLP]

  4. Programming and Performance Modelling of Automotive ECU Networks. [Citation Graph (, )][DBLP]

  5. Architecture Exploration for Low Power Design. [Citation Graph (, )][DBLP]

  6. Scan Delay Testing of Nanometer SoCs. [Citation Graph (, )][DBLP]

  7. Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. [Citation Graph (, )][DBLP]

  8. OpenSPARC - A Scalable Chip Multi-Threading Design. [Citation Graph (, )][DBLP]

  9. Implementing the Best Processor Cores. [Citation Graph (, )][DBLP]

  10. A Power Efficient Approach to Fault-Tolerant Register File Design. [Citation Graph (, )][DBLP]

  11. Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. [Citation Graph (, )][DBLP]

  12. Single Error Correcting Finite Field Multipliers Over GF(2m). [Citation Graph (, )][DBLP]

  13. A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. [Citation Graph (, )][DBLP]

  14. Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass. [Citation Graph (, )][DBLP]

  15. Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. [Citation Graph (, )][DBLP]

  16. Exploring the Processor and ISA Design for Wireless Sensor Network Applications. [Citation Graph (, )][DBLP]

  17. Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices. [Citation Graph (, )][DBLP]

  18. Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors. [Citation Graph (, )][DBLP]

  19. Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit. [Citation Graph (, )][DBLP]

  20. Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems. [Citation Graph (, )][DBLP]

  21. A Modeling of a Dynamically Reconfigurable Processor Using SystemC. [Citation Graph (, )][DBLP]

  22. A Scalable and Reconfigurable Coprocessor for Image Composition. [Citation Graph (, )][DBLP]

  23. Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]

  24. An Approach to Software Performance Evaluation on Customized Embedded Processors. [Citation Graph (, )][DBLP]

  25. Compact Modeling of Suspended Gate FET. [Citation Graph (, )][DBLP]

  26. Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]

  27. Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. [Citation Graph (, )][DBLP]

  28. NBTI Degradation: A Problem or a Scare? [Citation Graph (, )][DBLP]

  29. On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. [Citation Graph (, )][DBLP]

  30. On Common-Mode Skewed-Load and Broadside Tests. [Citation Graph (, )][DBLP]

  31. Testing Flash Memories for Tunnel Oxide Defects. [Citation Graph (, )][DBLP]

  32. On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. [Citation Graph (, )][DBLP]

  33. Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. [Citation Graph (, )][DBLP]

  34. Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. [Citation Graph (, )][DBLP]

  35. Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. [Citation Graph (, )][DBLP]

  36. A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. [Citation Graph (, )][DBLP]

  37. Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling. [Citation Graph (, )][DBLP]

  38. Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. [Citation Graph (, )][DBLP]

  39. Integrated TIA-Equalizer for High Speed Optical Link. [Citation Graph (, )][DBLP]

  40. Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. [Citation Graph (, )][DBLP]

  41. Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. [Citation Graph (, )][DBLP]

  42. Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation. [Citation Graph (, )][DBLP]

  43. Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. [Citation Graph (, )][DBLP]

  44. Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells. [Citation Graph (, )][DBLP]

  45. Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction. [Citation Graph (, )][DBLP]

  46. Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware. [Citation Graph (, )][DBLP]

  47. Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. [Citation Graph (, )][DBLP]

  48. An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies. [Citation Graph (, )][DBLP]

  49. A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. [Citation Graph (, )][DBLP]

  50. Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. [Citation Graph (, )][DBLP]

  51. Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. [Citation Graph (, )][DBLP]

  52. An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators. [Citation Graph (, )][DBLP]

  53. Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters. [Citation Graph (, )][DBLP]

  54. Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical Issues. [Citation Graph (, )][DBLP]

  55. A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation. [Citation Graph (, )][DBLP]

  56. VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair. [Citation Graph (, )][DBLP]

  57. A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier. [Citation Graph (, )][DBLP]

  58. A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts. [Citation Graph (, )][DBLP]

  59. An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning. [Citation Graph (, )][DBLP]

  60. Fast Congestion Aware Routing for Pin Assignment. [Citation Graph (, )][DBLP]

  61. A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. [Citation Graph (, )][DBLP]

  62. Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation. [Citation Graph (, )][DBLP]

  63. Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. [Citation Graph (, )][DBLP]

  64. Energy-Efficient, High Performance Circuits for Arithmetic Units. [Citation Graph (, )][DBLP]

  65. Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. [Citation Graph (, )][DBLP]

  66. A Robust Level-Shifter Design for Adaptive Voltage Scaling. [Citation Graph (, )][DBLP]

  67. Low Power Hardware Architecture for VBSME Using Pixel Truncation. [Citation Graph (, )][DBLP]

  68. MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks. [Citation Graph (, )][DBLP]

  69. MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method. [Citation Graph (, )][DBLP]

  70. An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. [Citation Graph (, )][DBLP]

  71. High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs. [Citation Graph (, )][DBLP]

  72. PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. [Citation Graph (, )][DBLP]

  73. Single Event Upset: An Embedded Tutorial. [Citation Graph (, )][DBLP]

  74. Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. [Citation Graph (, )][DBLP]

  75. Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. [Citation Graph (, )][DBLP]

  76. A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor. [Citation Graph (, )][DBLP]

  77. Design of Reversible Finite Field Arithmetic Circuits with Error Detection. [Citation Graph (, )][DBLP]

  78. Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. [Citation Graph (, )][DBLP]

  79. Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting. [Citation Graph (, )][DBLP]

  80. Formal Verification of a Public-Domain DDR2 Controller Design. [Citation Graph (, )][DBLP]

  81. Enhanced TED: A New Data Structure for RTL Verification. [Citation Graph (, )][DBLP]

  82. Simulation Acceleration with HW Re-Compilation Avoidance. [Citation Graph (, )][DBLP]

  83. A Module Checking Based Converter Synthesis Approach for SoCs. [Citation Graph (, )][DBLP]

  84. Energy Reduction in SRAM using Dynamic Voltage and Frequency Management. [Citation Graph (, )][DBLP]

  85. Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. [Citation Graph (, )][DBLP]

  86. Temperature and Process Variations Aware Power Gating of Functional Units. [Citation Graph (, )][DBLP]

  87. A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. [Citation Graph (, )][DBLP]

  88. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. [Citation Graph (, )][DBLP]

  89. Power Reduction of Functional Units Considering Temperature and Process Variations. [Citation Graph (, )][DBLP]

  90. Stall Power Reduction in Pipelined Architecture Processors. [Citation Graph (, )][DBLP]

  91. A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. [Citation Graph (, )][DBLP]

  92. Memory Architecture Exploration Framework for Cache Based Embedded SOC. [Citation Graph (, )][DBLP]

  93. A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. [Citation Graph (, )][DBLP]

  94. A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. [Citation Graph (, )][DBLP]

  95. A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. [Citation Graph (, )][DBLP]

  96. A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. [Citation Graph (, )][DBLP]

  97. GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes. [Citation Graph (, )][DBLP]

  98. Behavioral Modeling of a CMOS Compatible High Precision MEMS Based Electron Tunneling Accelerometer. [Citation Graph (, )][DBLP]

  99. An Optical Reconfiguration System with Four Contexts. [Citation Graph (, )][DBLP]

  100. An Acceleration and Optimization Method for Optical Reconfiguration. [Citation Graph (, )][DBLP]

  101. 0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. [Citation Graph (, )][DBLP]

  102. Variability-Tolerant Register-Transfer Level Synthesis. [Citation Graph (, )][DBLP]

  103. A Galois Field Based Logic Synthesis Approach with Testability. [Citation Graph (, )][DBLP]

  104. A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. [Citation Graph (, )][DBLP]

  105. Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. [Citation Graph (, )][DBLP]

  106. On the Use of Hash Tables for Efficient Analog Circuit Synthesis. [Citation Graph (, )][DBLP]

  107. An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. [Citation Graph (, )][DBLP]

  108. A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter. [Citation Graph (, )][DBLP]

  109. Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. [Citation Graph (, )][DBLP]

  110. Self-Sleep Buffer for Distributed MTCMOS Design. [Citation Graph (, )][DBLP]

  111. Power Management of Interactive 3D Games Using Frame Structures. [Citation Graph (, )][DBLP]

  112. Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. [Citation Graph (, )][DBLP]

  113. Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm. [Citation Graph (, )][DBLP]

  114. Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. [Citation Graph (, )][DBLP]

  115. Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier. [Citation Graph (, )][DBLP]

  116. Watermarking Video Clips with Workload Information for DVS. [Citation Graph (, )][DBLP]

  117. Throughput Efficient Parallel Implementation of SPIHT Algorithm. [Citation Graph (, )][DBLP]

  118. Standards in EDA: An Introduction. [Citation Graph (, )][DBLP]

  119. Industry Standards from Accellera. [Citation Graph (, )][DBLP]

  120. IEEE Market-Oriented Standards Process and the EDA Industry. [Citation Graph (, )][DBLP]

  121. Design Automation Standards: The IP Providers Perspective. [Citation Graph (, )][DBLP]

  122. Driving Analog Mixed Signal Verification through Verilog-AMS. [Citation Graph (, )][DBLP]

  123. VSI Standards, Current Status and Future Work. [Citation Graph (, )][DBLP]

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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002