Conferences in DBLP

VLSI Design (vlsid)
2010 (conf/vlsid/2010)

1. 
   Output-Dependent Diagnostic Test Generation. [Citation Graph (, )][DBLP]
   
   
2. 
   A Unified Solution to Scan Test Volume, Time, and Power Minimization. [Citation Graph (, )][DBLP]
   
   
3. 
   Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. [Citation Graph (, )][DBLP]
   
   
4. 
   A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET. [Citation Graph (, )][DBLP]
   
   
5. 
   Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP. [Citation Graph (, )][DBLP]
   
   
6. 
   Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. [Citation Graph (, )][DBLP]
   
   
7. 
   Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. [Citation Graph (, )][DBLP]
   
   
8. 
   A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. [Citation Graph (, )][DBLP]
   
   
9. 
   Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. [Citation Graph (, )][DBLP]
   
   
10. 
    Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs. [Citation Graph (, )][DBLP]
    
    
11. 
    A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods. [Citation Graph (, )][DBLP]
    
    
12. 
    Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips. [Citation Graph (, )][DBLP]
    
    
13. 
    Post Assembly Timing Closure for Multi Million Gate Chips. [Citation Graph (, )][DBLP]
    
    
14. 
    Synthesizability of 3 Party Formal Specifications-Does My Controller See Enough?. [Citation Graph (, )][DBLP]
    
    
15. 
    Channel Optimization for the Design of High Speed I/O links. [Citation Graph (, )][DBLP]
    
    
16. 
    An Efficient Design of a Reversible Barrel Shifter. [Citation Graph (, )][DBLP]
    
    
17. 
    A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. [Citation Graph (, )][DBLP]
    
    
18. 
    A Unified Approach for IP Protection across Design Phases in a Packaged Chip. [Citation Graph (, )][DBLP]
    
    
19. 
    Identifying the Bottlenecks to the RF Performance of FinFETs. [Citation Graph (, )][DBLP]
    
    
20. 
    A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories. [Citation Graph (, )][DBLP]
    
    
21. 
    Functional Refinement: A Generic Methodology for Managing ESL Abstractions. [Citation Graph (, )][DBLP]
    
    
22. 
    Safe-ERfair. [Citation Graph (, )][DBLP]
    
    
23. 
    Exploring Use of NoC for Reconfigurable Video Coding. [Citation Graph (, )][DBLP]
    
    
24. 
    Coverage Management with Inline Assertions and Formal Test Points. [Citation Graph (, )][DBLP]
    
    
25. 
    Instruction Selection in ASIP Synthesis Using Functional Matching. [Citation Graph (, )][DBLP]
    
    
26. 
    Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. [Citation Graph (, )][DBLP]
    
    
27. 
    Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting. [Citation Graph (, )][DBLP]
    
    
28. 
    Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer. [Citation Graph (, )][DBLP]
    
    
29. 
    Modeling of RF- MEMS BAW Resonator. [Citation Graph (, )][DBLP]
    
    
30. 
    Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. [Citation Graph (, )][DBLP]
    
    
31. 
    23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently. [Citation Graph (, )][DBLP]
    
    
32. 
    Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Processes. [Citation Graph (, )][DBLP]
    
    
33. 
    RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications. [Citation Graph (, )][DBLP]
    
    
34. 
    Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. [Citation Graph (, )][DBLP]
    
    
35. 
    Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. [Citation Graph (, )][DBLP]
    
    
36. 
    Modeling of High Frequency Noise in SOI MOSFETs. [Citation Graph (, )][DBLP]
    
    
37. 
    Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. [Citation Graph (, )][DBLP]
    
    
38. 
    On Electrical Modeling of Imperfect Diffusion Patterning. [Citation Graph (, )][DBLP]
    
    
39. 
    A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications. [Citation Graph (, )][DBLP]
    
    
40. 
    Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. [Citation Graph (, )][DBLP]
    
    
41. 
    An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling. [Citation Graph (, )][DBLP]
    
    
42. 
    High Speed Serial Link Transmitter for 10Gig Ethernet Applications. [Citation Graph (, )][DBLP]
    
    
43. 
    A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. [Citation Graph (, )][DBLP]
    
    
44. 
    A Reconfigurable Architecture for Secure Multimedia Delivery. [Citation Graph (, )][DBLP]
    
    
45. 
    A Hardware Scheduler for Real Time Multiprocessor System on Chip. [Citation Graph (, )][DBLP]
    
    
46. 
    Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. [Citation Graph (, )][DBLP]
    
    
47. 
    Impact of Temperature on Test Quality. [Citation Graph (, )][DBLP]
    
    
48. 
    A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. [Citation Graph (, )][DBLP]
    
    
49. 
    Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. [Citation Graph (, )][DBLP]
    
    
50. 
    An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. [Citation Graph (, )][DBLP]
    
    
51. 
    High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. [Citation Graph (, )][DBLP]
    
    
52. 
    Pinpointing Cache Timing Attacks on AES. [Citation Graph (, )][DBLP]
    
    
53. 
    A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process. [Citation Graph (, )][DBLP]
    
    
54. 
    A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. [Citation Graph (, )][DBLP]
    
    
55. 
    On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme. [Citation Graph (, )][DBLP]
    
    
56. 
    4 GHz 130nm Low Voltage PLL Based on Self Biased Technique. [Citation Graph (, )][DBLP]
    
    
57. 
    An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. [Citation Graph (, )][DBLP]
    
    
58. 
    Clocking-Based Coplanar Wire Crossing Scheme for QCA. [Citation Graph (, )][DBLP]
    
    
59. 
    Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. [Citation Graph (, )][DBLP]
    
    
60. 
    Synchronized Generation of Directed Tests Using Satisfiability Solving. [Citation Graph (, )][DBLP]
    
    
61. 
    Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. [Citation Graph (, )][DBLP]
    
    
62. 
    An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters. [Citation Graph (, )][DBLP]
    
    
63. 
    Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation. [Citation Graph (, )][DBLP]
    
    
64. 
    Rethinking Threshold Voltage Assignment in 3D Multicore Designs. [Citation Graph (, )][DBLP]
    
    
65. 
    Towards Active-Passive Co-synthesis of Multi-gigaHertz Radio Frequency Circuits. [Citation Graph (, )][DBLP]
    
    
66. 
    Optical Lithography Simulation with Focus Variation using Wavelet Transform. [Citation Graph (, )][DBLP]
    
    
67. 
    On Minimization of Test Application Time for RAS. [Citation Graph (, )][DBLP]
    
    
68. 
    Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. [Citation Graph (, )][DBLP]
    
    
69. 
    RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. [Citation Graph (, )][DBLP]
    
    
70. 
    An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. [Citation Graph (, )][DBLP]
    
    
71. 
    Front-End Design Flows for Systems on Chip: An Embedded Tutorial. [Citation Graph (, )][DBLP]
    
    
72. 
    Electrical Modeling of Lithographic Imperfections. [Citation Graph (, )][DBLP]
    
    
73. 
    The Dawn of 22nm Era: Design and CAD Challenges. [Citation Graph (, )][DBLP]
    
    
74. 
    Robust System Design. [Citation Graph (, )][DBLP]
    
    
75. 
    FinFET SRAM Design. [Citation Graph (, )][DBLP]
    
    
76. 
    Processor Architecture Design Using 3D Integration Technology. [Citation Graph (, )][DBLP]
    
    
77. 
    Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore. [Citation Graph (, )][DBLP]
    
    
78. 
    Video Coding Tools and Their Impact on Compression Engine Architecture. [Citation Graph (, )][DBLP]
    
    
79. 
    Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. [Citation Graph (, )][DBLP]