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Conferences in DBLP

International Conference on Computer Design (cdes)
2005 (conf/cdes/2005)

  1. Keith Whisnant, Kenny Gross, Natasha Lingurovska
    Proactive Fault Monitoring in Enterprise Servers. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:3-10 [Conf]
  2. Anton Bougaev, Brian Mariner, Joshua Walter
    Estimation of Architectural Vulnerability Factors for Discrimination of Single Event Upsets in Cache Memory. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:11-20 [Conf]
  3. Waleed Al-Assadi, Pavankumar Chandrasekhar, Bonita Bhaskaran
    Fault Modeling and Testability of CMOS Domino Circuits. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:21-27 [Conf]
  4. Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias
    Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:28-34 [Conf]
  5. Bonita Bhaskaran, Venkat Satagopan, Scott Smith
    High-Speed Energy Estimation for Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:35-41 [Conf]
  6. Derek Nowrouzezahrai, Brian Decker, William Bishop
    High-Performance Double-Precision Cosine Generation. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:42-48 [Conf]
  7. Eugin Hyun, Kyo-Yong Han, Kwang-Su Seong
    Design of PCI 2.2 Target Controller to Support Prefetch Request. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:49-58 [Conf]
  8. Koert Vlaeminck, Tim Stevens, Wim Van de Meerssche, Filip De Turck, Bart Dhoedt, Piet Demeester
    Implementation of Network Systems Using Network Processor Technology: Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:59-63 [Conf]
  9. Lubomir Ivanov
    Modeling and Verification of a Distributed Transmission Protocol. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:64-70 [Conf]
  10. Eugin Hyun, Kwang-Su Seong
    Design and Verification of I/O Controller for Future Communication System. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:71-77 [Conf]
  11. Bonita Bhaskaran, Venkat Satagopan, Waleed Al-Assadi, Scott Smith
    Implementation of Design For Test for Asynchronous NCL Designs. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:78-84 [Conf]
  12. Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia
    Verilog Coding Style for Efficient Synthesis In FPGA. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:85-90 [Conf]
  13. Hector Arteaga, Hussain Al-Asaad
    On Increasing the Observability of Modern Microprocessors. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:91-96 [Conf]
  14. Jin Liu, José G. Delgado-Frias
    DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:97-103 [Conf]
  15. Yil Suk Yang, Tae Moon Roh, Dae Woo Lee, Woo Hyun Kwon, Jongdae Kim
    On-Chip Split Shared Data Bus Architecture for SoC. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:104-108 [Conf]
  16. Waleed Al-Assadi, Thomas Dick
    Design for Test Methodology for the IBM PowerPC 440 Embedded Core. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:109-114 [Conf]
  17. Anshul Singh, Scott Smith
    Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:115-121 [Conf]
  18. David Zier, Jarrod Nelson, Ben Lee
    NetSin: An Object-Oriented Architectural Simulator Suite. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:122-128 [Conf]
  19. Hussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez
    A Novel Functional Testing and Verification Technique for Logic Circuits. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:129-135 [Conf]
  20. Jaafar Alghazo, Nazeih Botros
    Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:136-142 [Conf]
  21. Arun Vijayaraghavan, M. Kannan, R. Seshasayanan
    Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:143-152 [Conf]
  22. Jinwoo Kim, Kiran Puttaswamy
    Possibility and Limitation of a Hardware-Assisted Data Prefetching Framework Using Off-Line Training of Markovian Predictors. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:153-158 [Conf]
  23. Mitchell J. Myjak, José G. Delgado-Frias
    A Symmetric Differential Clock Generator for Bit-Serial Hardware. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:159-164 [Conf]
  24. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Design for A Fast And Low Power 2's Complement Multiplier. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:165-167 [Conf]
  25. Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura
    An Operand Status Based Instruction Steering Scheme for Clustered Architectures. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:168-174 [Conf]
  26. Martin Uhl
    On Operating System Basic Building Blocks. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:175-184 [Conf]
  27. Daniel Pittman, Dennis Edwards
    Space and Time Efficient Lottery Scheduling. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:185-190 [Conf]
  28. Suryanarayana Tatapudi, José G. Delgado-Frias
    A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:191-197 [Conf]
  29. Chung-Chin Luo, Yuan-Shin Hwang, Gene Eu Jan
    Minimal Steiner Trees in X Architecture with Obstacles. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:198-203 [Conf]
  30. Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu
    Low-Power Data Address Bus Encoding Method. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:204-210 [Conf]
  31. Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen
    Low-Power Branch Prediction. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:211-217 [Conf]
  32. Jiann S. Yuan, Jia Di
    Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:218-223 [Conf]
  33. Viktor Bunimov, Manfred Schimmler
    Completely Redundant Modular Exponentiation by Operand Changing. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:224-232 [Conf]
  34. Alexander Usynin, Wesley Hines
    Use of Kernel (Regression) Based Methods for Sensor Validation. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:233-239 [Conf]
  35. Kenny C. Gross, Eugenio Schuster
    Spectral Decomposition and Reconstruction of Telemetry Signals from Enterprise Computing Systems. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:240-246 [Conf]
  36. Kalyan Vaidyanathan, Kenny Gross
    Monte Carlo Simulation For Optimized Sensitivity of Online Proactive Fault Monitoring Schemes. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:247-252 [Conf]
  37. Hsun-Jung Cho, Ming-Te Tseng
    A System-on-Chip Approach to Intelligent Traffic Signal Control. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:253-0 [Conf]
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