Conferences in DBLP

IEEE VLSI Test Symposium (vts)
2008 (conf/vts/2008)

1. 
   Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems. [Citation Graph (, )][DBLP]
   
   
2. 
   Test Enabled Process Tuning for Adaptive Baseband OFDM Processor. [Citation Graph (, )][DBLP]
   
   
3. 
   Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links. [Citation Graph (, )][DBLP]
   
   
4. 
   How Many Test Patterns are Useless? [Citation Graph (, )][DBLP]
   
   
5. 
   Constructing Augmented Multimode Compactors. [Citation Graph (, )][DBLP]
   
   
6. 
   Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. [Citation Graph (, )][DBLP]
   
   
7. 
   Inconsistent Fail due to Limited Tester Timing Accuracy. [Citation Graph (, )][DBLP]
   
   
8. 
   A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. [Citation Graph (, )][DBLP]
   
   
9. 
   Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). [Citation Graph (, )][DBLP]
   
   
10. 
    Diagnosis of Scan Clock Failures. [Citation Graph (, )][DBLP]
    
    
11. 
    An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation. [Citation Graph (, )][DBLP]
    
    
12. 
    On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. [Citation Graph (, )][DBLP]
    
    
13. 
    An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. [Citation Graph (, )][DBLP]
    
    
14. 
    An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. [Citation Graph (, )][DBLP]
    
    
15. 
    Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. [Citation Graph (, )][DBLP]
    
    
16. 
    Gate-Oxide Early Life Failure Prediction. [Citation Graph (, )][DBLP]
    
    
17. 
    Full Open Defects in Nanometric CMOS. [Citation Graph (, )][DBLP]
    
    
18. 
    Signature Rollback - A Technique for Testing Robust Circuits. [Citation Graph (, )][DBLP]
    
    
19. 
    Bounded Adjacent Fill for Low Capture Power Scan Testing. [Citation Graph (, )][DBLP]
    
    
20. 
    Reducing Scan Shift Power at RTL. [Citation Graph (, )][DBLP]
    
    
21. 
    Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. [Citation Graph (, )][DBLP]
    
    
22. 
    A Time-Domain Method for Pseudo-Spectral Characterization. [Citation Graph (, )][DBLP]
    
    
23. 
    A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. [Citation Graph (, )][DBLP]
    
    
24. 
    Fast Accurate Tests for Multi-Carrier Transceiver Specifications: EVM and Noise. [Citation Graph (, )][DBLP]
    
    
25. 
    Automatic Test Pattern Generation for Interconnect Open Defects. [Citation Graph (, )][DBLP]
    
    
26. 
    On the Relaxation of n-detect Test Sets. [Citation Graph (, )][DBLP]
    
    
27. 
    Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. [Citation Graph (, )][DBLP]
    
    
28. 
    Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. [Citation Graph (, )][DBLP]
    
    
29. 
    Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers. [Citation Graph (, )][DBLP]
    
    
30. 
    ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-Ends. [Citation Graph (, )][DBLP]
    
    
31. 
    Synthesis for Broadside Testability of Transition Faults. [Citation Graph (, )][DBLP]
    
    
32. 
    LS-TDF: Low-Switching Transition Delay Fault Pattern Generation. [Citation Graph (, )][DBLP]
    
    
33. 
    Test-Pattern Grading and Pattern Selection for Small-Delay Defects. [Citation Graph (, )][DBLP]
    
    
34. 
    Dynamic Compaction for High Quality Delay Test. [Citation Graph (, )][DBLP]
    
    
35. 
    An All-Digital High-Precision Built-In Delay Time Measurement Circuit. [Citation Graph (, )][DBLP]
    
    
36. 
    Error Sequence Analysis. [Citation Graph (, )][DBLP]
    
    
37. 
    QBIST: Quantum Built-in Self-Test for any Boolean Circuit. [Citation Graph (, )][DBLP]
    
    
38. 
    A Statistical Approach to Characterizing and Testing Functionalized Nanowires. [Citation Graph (, )][DBLP]
    
    
39. 
    A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies. [Citation Graph (, )][DBLP]
    
    
40. 
    Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. [Citation Graph (, )][DBLP]
    
    
41. 
    Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. [Citation Graph (, )][DBLP]
    
    
42. 
    Parallel Loopback Test of Mixed-Signal Circuits. [Citation Graph (, )][DBLP]
    
    
43. 
    Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. [Citation Graph (, )][DBLP]
    
    
44. 
    A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. [Citation Graph (, )][DBLP]
    
    
45. 
    Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. [Citation Graph (, )][DBLP]
    
    
46. 
    Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. [Citation Graph (, )][DBLP]
    
    
47. 
    Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. [Citation Graph (, )][DBLP]
    
    
48. 
    A General Failure Candidate Ranking Framework for Silicon Debug. [Citation Graph (, )][DBLP]
    
    
49. 
    Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. [Citation Graph (, )][DBLP]
    
    
50. 
    Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors. [Citation Graph (, )][DBLP]
    
    
51. 
    Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. [Citation Graph (, )][DBLP]
    
    
52. 
    Multiple Coupling Effects Oriented Path Delay Test Generation. [Citation Graph (, )][DBLP]
    
    
53. 
    A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. [Citation Graph (, )][DBLP]
    
    
54. 
    An Industrial Case Study of Sticky Path-Delay Faults. [Citation Graph (, )][DBLP]