Conferences in DBLP
Michael Gschwind Chip multiprocessing and the cell broadband engine. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Williams , John Shalf , Leonid Oliker , Shoaib Kamil , Parry Husbands , Katherine A. Yelick The potential of the cell processor for scientific computing. [Citation Graph (0, 0)][DBLP ] Conf ] Iyad Al Khatib , Davide Bertozzi , Francesco Poletti , Luca Benini , Axel Jantsch , Mohamed Bechara , Hasan Khalifeh , Mazen Hajjar , Rustam Nabiev , Sven Jonsson MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michela Becchi , Patrick Crowley Dynamic thread assignment on heterogeneous multiprocessor architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Juan del Cuvillo , Weirong Zhu , Guang R. Gao Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Panagiotis Tsarchopoulos Current and future research directions in embedded systems: a european perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Arnab Bhattacharyya Morphogenesis as an amorphous computation. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Mehrnoosh Eshaghian-Wilner , Alexander Khitun , Shiva Navab , Kang L. Wang A nano-scale reconfigurable mesh with spin waves. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Udrescu , Lucian Prodan , Mircea Vladutiu Implementing quantum genetic algorithms: a solution based on Grover's algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] John Oliver , Ravishankar Rao , Michael Brown , Jennifer Mankin , Diana Franklin , Frederic T. Chong , Venkatesh Akella Tile size selection for low-power tile-based architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Waldman , Shlomit S. Pinter Profile-driven compression scheme for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Woo Son , Mahmut T. Kandemir Energy-aware data prefetching for multi-speed disks. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan W. Mills , Matt Parker , Bryce Himebaugh , Craig Shue , Brian Kopecky , Chris Weilemann "Empty space" computes: the evolution of an unconventional supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Efe Yardimci , Michael Franz Dynamic parallelization and mapping of binary executables on hierarchical platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Hitoshi Oi Instruction folding in a hardware-translation based java virtual machine. [Citation Graph (0, 0)][DBLP ] Conf ] Sid Ahmed Ali Touati , Denis Barthou On the decidability of phase ordering problem in optimizing compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Guangyu Chen , Mahmut T. Kandemir Multi-compilation: capturing interactions among concurrently-executing applications. [Citation Graph (0, 0)][DBLP ] Conf ] Igino Folcarelli , Alex Susu , Ties Kluter , Giovanni De Micheli , Andrea Acquaviva An opportunistic reconfiguration strategy for environmentally powered devices. [Citation Graph (0, 0)][DBLP ] Conf ] Emil A. Stoyanov , Markus Alexander Wischy , Dieter Roller Using managed communication channels in software components. [Citation Graph (0, 0)][DBLP ] Conf ] Lucian Prodan , Mihai Udrescu , Mircea Vladutiu A dependability perspective on emerging technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Tempesti , Daniel Mange , Pierre-André Mudry , Joël Rossier , André Stauffer Self-replication for reliability: bio-inspired hardware and the embryonics project. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew M. Tyrrell Dependability in an evolving world. [Citation Graph (0, 0)][DBLP ] Conf ] Lukás Sekanina On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Manojkumar Krishnan , Jarek Nieplocha Memory efficient parallel matrix multiplication operation for irregular problems. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Garcia , Henry F. Korth Database hash-join algorithms on multithreaded computer architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Asadollah Shahbahrami , Ben H. H. Juurlink , Stamatis Vassiliadis Improving the memory behavior of vertical filtering in the discrete wavelet transform. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Bitonti , Tamás Kiss , Gábor Terstyánszky , Thierry Delaitre , Stephen C. Winter , Péter Kacsuk Dynamic testing of legacy code resources on the grid. [Citation Graph (0, 0)][DBLP ] Conf ] Tanausú Ramírez , Alex Pajuelo , Oliverio J. Santana , Mateo Valero Kilo-instruction processors, runahead and prefetching. [Citation Graph (0, 0)][DBLP ] Conf ] Sailesh Kumar , John Maschmeyer , Patrick Crowley Exploiting locality to ameliorate packet queue contention and serialization. [Citation Graph (0, 0)][DBLP ] Conf ] Jesús Alastruey , Teresa Monreal , Víctor Viñals , Mateo Valero Speculative early register release. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff H. Derby , Robert K. Montoye , José Moreira VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Hartstein , Viji Srinivasan , Thomas R. Puzak , Philip G. Emma Cache miss behavior: is it sqrt(2)? [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Ros , Manuel E. Acacio , José M. García An efficient cache design for scalable glueless shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Farshad Khunjush , Nikitas J. Dimopoulos Lazy direct-to-cache transfer during receive operations in a message passing environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jaeheon Jeong , Per Stenström , Michel Dubois Simple penalty-sensitive replacement policies for caches. [Citation Graph (0, 0)][DBLP ] Conf ] Anca Mariana Molnos , Sorin Dan Cotofana , Marc J. M. Heijligers , Jos T. J. van Eijndhoven Static cache partitioning robustness analysis for embedded on-chip multi-processors. [Citation Graph (0, 0)][DBLP ] Conf ] Domingo Benitez , Juan C. Moure , Dolores Rexachs , Emilio Luque Evaluation of the field-programmable cache: performance and energy consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Kristof Beyls , Erik H. D'Hollander Intermediately executed code is the key to find refactorings that improve temporal data locality. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel G. Chavarría-Miranda , Jarek Nieplocha , Vinod Tipparaju Topology-aware tile mapping for clusters of SMPs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael L. Welcome , Charles A. Rendleman , Leonid Oliker , Rupak Biswas Performance characteristics of an adaptive mesh refinement calculation on scalar and vector platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Kalte , Mario Porrmann REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] 