Conferences in DBLP
Pratap Pattnaik Recent technological trends and their impact on system design. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas R. Puzak , Allan Hartstein , Philip G. Emma , Viji Srinivasan , Jim Mitchell An analysis of the effects of miss clustering on the cost of a cache miss. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald G. Dreslinski , Ali G. Saidi , Trevor N. Mudge , Steven K. Reinhardt Analysis of hardware prefetching across virtual page boundaries. [Citation Graph (0, 0)][DBLP ] Conf ] Albert Meixner , Daniel J. Sorin Unified microprocessor core storage. [Citation Graph (0, 0)][DBLP ] Conf ] Weidong Shi , Hsien-Hsin S. Lee Accelerating memory decryption and authentication with frequent value prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Jarek Nieplocha , Andrès Márquez , John Feo , Daniel G. Chavarría-Miranda , George Chin , Chad Scherrer , Nathaniel Beagley Evaluating the potential of multithreaded platforms for irregular scientific computations. [Citation Graph (0, 0)][DBLP ] Conf ] Oystein Thorsen , Brian Smith , Carlos P. Sosa , Karl Jiang , Heshan Lin , Amanda Peters , Wu-chun Feng Parallel genomic sequence-search on a massively parallel system. [Citation Graph (0, 0)][DBLP ] Conf ] Kalyan S. Perumalla Scaling time warp-based discrete event execution to 104 processors on a Blue Gene supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Sarah E. Murphy , Erik DeBenedictis , Peter M. Kogge General floorplan for reversible quantum-dot cellular automata. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Whitney , Nemanja Isailovic , Yatish Patel , John Kubiatowicz Automated generation of layout and control for quantum circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gianfranco Bilardi Models for parallel and hierarchical computation. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Vandierendonck , Philippe Manet , Thibault Delavallee , Igor Loiselle , Jean-Didier Legat By-passing the out-of-order execution pipeline to increase energy-efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Kaveh Aasaraai , Amirali Baniasadi , Ehsan Atoofian Computational and storage power optimizations for the O-GEHL branch predictor. [Citation Graph (0, 0)][DBLP ] Conf ] Juan M. Cebrian , Juan L. Aragón , José M. García , Stefanos Kaxiras Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Sasaki , Yoshimichi Ikeda , Masaaki Kondo , Hiroshi Nakamura An intra-task dvfs technique based on statistical analysis of hardware events. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Dubach , John Cavazos , Björn Franke , Grigori Fursin , Michael F. P. O'Boyle , Olivier Temam Fast compiler optimisation evaluation using code-feature based performance prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Tipp Moseley , Daniel A. Connors , Dirk Grunwald , Ramesh Peri Identifying potential parallelism via loop-centric profiling. [Citation Graph (0, 0)][DBLP ] Conf ] Geoffroy Vallée , Thomas Naughton , Stephen L. Scott System management software for virtual environments. [Citation Graph (0, 0)][DBLP ] Conf ] Grigoris Dimitroulakos , Michalis D. Galanis , Nikos Kostaras , Costas E. Goutis A unified evaluation framework for coarse grained reconfigurable array architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel G. Chavarria-Miranda , Andres Marquez Assessing the potential of hybrid hpc systems for scientific applications: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Shoaib Kamil , Ali Pinar , Daniel Gunter , Michael Lijewski , Leonid Oliker , John Shalf Reconfigurable hybrid interconnection for static and dynamic scientific applications. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Jorrand The quantum challenge to computer science. [Citation Graph (0, 0)][DBLP ] Conf ] Shinichi Yamagiwa , Leonel Sousa Design and implementation of a stream-based distributedcomputing platform using graphics processing units. [Citation Graph (0, 0)][DBLP ] Conf ] Shinichi Yamagiwa , Leonel Sousa , Diogo Antão Data buffering optimization methods toward a uniform programming interface for gpu-based applications. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Amamiya , Masaaki Izumi , Takanori Matsuzaki , Ryuzo Hasegawa , Makoto Amamiya Fuce: the continuation-based multithreading processor. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Kusakabe , Mitsuhiro Aono , Masaaki Izumi , Satoshi Amamiya , Yoshinari Nomura , Hideo Taniguchi , Makoto Amamiya Scalability of continuation-based fine-grained multithreading in handling multiple I/O requests on FUCE. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew E. Tolentino , Joseph Turner , Kirk W. Cameron Memory-miser: a performance-constrained runtime system for power-scalable clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Michela Becchi , Mark A. Franklin , Patrick Crowley Performance/area efficiency in chip multiprocessors with micro-caches. [Citation Graph (0, 0)][DBLP ] Conf ] Ehsan Atoofian , Amirali Baniasadi , Kaveh Aasaraai Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Tirath Ramdas , Gregory K. Egan , David Abramson , Kim Baldridge Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Marquet , Simon Duquennoy , Sébastien Le Beux , Samy Meftali , Jean-Luc Dekeyser Massively parallel processing on a chip. [Citation Graph (0, 0)][DBLP ] Conf ] 