Conferences in DBLP

(ancs)
2007 (conf/ancs/2007)

1. 
   Ruler: high-speed packet matching and rewriting on NPUs. [Citation Graph (, )][DBLP]
   
   
2. 
   Optimization of pattern matching algorithm for memory based architecture. [Citation Graph (, )][DBLP]
   
   
3. 
   Towards high-performance flow-level packet processing on multi-core network processors. [Citation Graph (, )][DBLP]
   
   
4. 
   Frame shared memory: line-rate networking on commodity hardware. [Citation Graph (, )][DBLP]
   
   
5. 
   Experimental evaluation of a coarse-grained switch scheduler. [Citation Graph (, )][DBLP]
   
   
6. 
   Design of a network architecture with inherent data path security. [Citation Graph (, )][DBLP]
   
   
7. 
   Experimenting with buffer sizes in routers. [Citation Graph (, )][DBLP]
   
   
8. 
   To CMP or not to CMP: analyzing packet classification on modern and traditional parallel architectures. [Citation Graph (, )][DBLP]
   
   
9. 
   Flow-slice: a novel load-balancing scheme for multi-path switching systems. [Citation Graph (, )][DBLP]
   
   
10. 
    Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. [Citation Graph (, )][DBLP]
    
    
11. 
    Performance scalability of a multi-core web server. [Citation Graph (, )][DBLP]
    
    
12. 
    Automated task distribution in multicore network processors using statistical analysis. [Citation Graph (, )][DBLP]
    
    
13. 
    Optimal packet scheduling in output-buffered optical switches with limited-range wavelength conversion. [Citation Graph (, )][DBLP]
    
    
14. 
    Low-latency scheduling in large switches. [Citation Graph (, )][DBLP]
    
    
15. 
    On LID assignment in infiniBand networks. [Citation Graph (, )][DBLP]
    
    
16. 
    Frame-aggregated concurrent matching switch. [Citation Graph (, )][DBLP]
    
    
17. 
    Congestion management for non-blocking clos networks. [Citation Graph (, )][DBLP]
    
    
18. 
    Compiling PCRE to FPGA for accelerating SNORT IDS. [Citation Graph (, )][DBLP]
    
    
19. 
    High-speed packet classification using binary search on length. [Citation Graph (, )][DBLP]
    
    
20. 
    An improved algorithm to accelerate regular expression evaluation. [Citation Graph (, )][DBLP]
    
    
21. 
    Curing regular expressions matching algorithms from insomnia, amnesia, and acalculia. [Citation Graph (, )][DBLP]
    
    
22. 
    Enhancing interoperability and stateful analysis of cooperative network intrusion detection systems. [Citation Graph (, )][DBLP]
    
    
23. 
    High-speed detection of unsolicited bulk emails. [Citation Graph (, )][DBLP]
    
    
24. 
    A programmable message classification engine for session initiation protocol (SIP). [Citation Graph (, )][DBLP]
    
    
25. 
    DPICO: a high speed deep packet inspection engine using compact finite automata. [Citation Graph (, )][DBLP]