Conferences in DBLP

(arc)
2008 (conf/arc/2008)

1. 
   Synthesizing FPGA Circuits from Parallel Programs. [Citation Graph (, )][DBLP]
   
   
2. 
   From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing. [Citation Graph (, )][DBLP]
   
   
3. 
   The von Neumann Syndrome and the CS Education Dilemma. [Citation Graph (, )][DBLP]
   
   
4. 
   Optimal Unroll Factor for Reconfigurable Architectures. [Citation Graph (, )][DBLP]
   
   
5. 
   Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems. [Citation Graph (, )][DBLP]
   
   
6. 
   DNA Physical Mapping on a Reconfigurable Platform. [Citation Graph (, )][DBLP]
   
   
7. 
   Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension. [Citation Graph (, )][DBLP]
   
   
8. 
   Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs. [Citation Graph (, )][DBLP]
   
   
9. 
   A Custom Processor for a TDMA Solver in a CFD Application. [Citation Graph (, )][DBLP]
   
   
10. 
    A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. [Citation Graph (, )][DBLP]
    
    
11. 
    Physical Design of FPGA Interconnect to Prevent Information Leakage. [Citation Graph (, )][DBLP]
    
    
12. 
    Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. [Citation Graph (, )][DBLP]
    
    
13. 
    Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. [Citation Graph (, )][DBLP]
    
    
14. 
    FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. [Citation Graph (, )][DBLP]
    
    
15. 
    A Parallel Hardware Architecture for Image Feature Detection. [Citation Graph (, )][DBLP]
    
    
16. 
    Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. [Citation Graph (, )][DBLP]
    
    
17. 
    A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems. [Citation Graph (, )][DBLP]
    
    
18. 
    A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]
    
    
19. 
    Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens. [Citation Graph (, )][DBLP]
    
    
20. 
    ARISE Machines: Extending Processors with Hybrid Accelerators. [Citation Graph (, )][DBLP]
    
    
21. 
    The Instruction-Set Extension Problem: A Survey. [Citation Graph (, )][DBLP]
    
    
22. 
    An FPGA run-time parameterisable Log-Normal Random Number Generator. [Citation Graph (, )][DBLP]
    
    
23. 
    Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. [Citation Graph (, )][DBLP]
    
    
24. 
    Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. [Citation Graph (, )][DBLP]
    
    
25. 
    Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. [Citation Graph (, )][DBLP]
    
    
26. 
    Multiplier-based double precision floating point divider according to the IEEE-754 standard. [Citation Graph (, )][DBLP]
    
    
27. 
    Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable ALTIX System Infrastructure and Benchmarking Life-Science Applications. [Citation Graph (, )][DBLP]
    
    
28. 
    Highly efficient structure of 64-bit exponential function implemented in FPGAs. [Citation Graph (, )][DBLP]
    
    
29. 
    A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures. [Citation Graph (, )][DBLP]
    
    
30. 
    PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. [Citation Graph (, )][DBLP]
    
    
31. 
    Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on Chip. [Citation Graph (, )][DBLP]
    
    
32. 
    Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. [Citation Graph (, )][DBLP]
    
    
33. 
    Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. [Citation Graph (, )][DBLP]
    
    
34. 
    Data reallocation by exploiting FPGA configuration mechanisms. [Citation Graph (, )][DBLP]
    
    
35. 
    A Networked, Lightweight and Partially Reconfigurable Platform. [Citation Graph (, )][DBLP]
    
    
36. 
    Neuromolecularware -- A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis. [Citation Graph (, )][DBLP]
    
    
37. 
    An FPGA Configuration Scheme for Bitstream Protection. [Citation Graph (, )][DBLP]
    
    
38. 
    Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]