Conferences in DBLP

(ets)
2010 (conf/ets/2010)

1. 
   Plenary presentations: Keynote: The product complexity and test - How product complexity impacts test industry. [Citation Graph (, )][DBLP]
   
   
2. 
   Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance. [Citation Graph (, )][DBLP]
   
   
3. 
   Adaptive test directions. [Citation Graph (, )][DBLP]
   
   
4. 
   Production test challenges for highly integrated mobile phone SOCs - A case study. [Citation Graph (, )][DBLP]
   
   
5. 
   Test-architecture optimization for TSV-based 3D stacked ICs. [Citation Graph (, )][DBLP]
   
   
6. 
   A low-cost and scalable test architecture for multi-core chips. [Citation Graph (, )][DBLP]
   
   
7. 
   On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. [Citation Graph (, )][DBLP]
   
   
8. 
   On the use of standard digital ATE for the analysis of RF signals. [Citation Graph (, )][DBLP]
   
   
9. 
   Sensors for built-in alternate RF test. [Citation Graph (, )][DBLP]
   
   
10. 
    Low-cost signature test of RF blocks based on envelope response analysis. [Citation Graph (, )][DBLP]
    
    
11. 
    Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. [Citation Graph (, )][DBLP]
    
    
12. 
    Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. [Citation Graph (, )][DBLP]
    
    
13. 
    A low-cost built-in self-test scheme for an array of memories. [Citation Graph (, )][DBLP]
    
    
14. 
    A two-layer SPICE model of the ATMEL TSTAC^TM eFlash memory technology for defect injection and faulty behavior prediction. [Citation Graph (, )][DBLP]
    
    
15. 
    A transient error tolerant self-timed asynchronous architecture. [Citation Graph (, )][DBLP]
    
    
16. 
    Multiple fault diagnosis in crossbar nano-architectures. [Citation Graph (, )][DBLP]
    
    
17. 
    Full-circuit SPICE simulation based validation of dynamic delay estimation. [Citation Graph (, )][DBLP]
    
    
18. 
    On estimation of NBTI-Induced delay degradation. [Citation Graph (, )][DBLP]
    
    
19. 
    Modified T-Flip-Flop based scan cell for RAS. [Citation Graph (, )][DBLP]
    
    
20. 
    Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. [Citation Graph (, )][DBLP]
    
    
21. 
    Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. [Citation Graph (, )][DBLP]
    
    
22. 
    Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. [Citation Graph (, )][DBLP]
    
    
23. 
    A reconfigurable online BIST for combinational hardware using digital neural networks. [Citation Graph (, )][DBLP]
    
    
24. 
    A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. [Citation Graph (, )][DBLP]
    
    
25. 
    Constructing augmented time compactors. [Citation Graph (, )][DBLP]
    
    
26. 
    Predicting dynamic specifications of ADCs with a low-quality digital input signal. [Citation Graph (, )][DBLP]
    
    
27. 
    Test of embedded analog circuits based on a built-in current sensor. [Citation Graph (, )][DBLP]
    
    
28. 
    Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications. [Citation Graph (, )][DBLP]
    
    
29. 
    Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. [Citation Graph (, )][DBLP]
    
    
30. 
    A distributed architecture to check global properties for post-silicon debug. [Citation Graph (, )][DBLP]
    
    
31. 
    Automated conformance evaluation of SystemC designs using timed automata. [Citation Graph (, )][DBLP]
    
    
32. 
    A software-based self-test methodology for system peripherals. [Citation Graph (, )][DBLP]
    
    
33. 
    Microprocessor fault-tolerance via on-the-fly partial reconfiguration. [Citation Graph (, )][DBLP]
    
    
34. 
    Scan based speed-path debug for a microprocessor. [Citation Graph (, )][DBLP]
    
    
35. 
    An integrated flow for the design of hardened circuits on SRAM-based FPGAs. [Citation Graph (, )][DBLP]
    
    
36. 
    Diagnosis of failing scan cells through orthogonal response compaction. [Citation Graph (, )][DBLP]
    
    
37. 
    An adaptive tester architecture for volume diagnosis. [Citation Graph (, )][DBLP]
    
    
38. 
    Diagnosis of full open defects in interconnect lines with fan-out. [Citation Graph (, )][DBLP]
    
    
39. 
    Input test data volume reduction based on test vector chains. [Citation Graph (, )][DBLP]
    
    
40. 
    On measurement uncertainty of ADC nonlinearities in oscillation-based test. [Citation Graph (, )][DBLP]
    
    
41. 
    Fast simulation based testing of anti-tearing mechanisms for small embedded systems. [Citation Graph (, )][DBLP]
    
    
42. 
    New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. [Citation Graph (, )][DBLP]
    
    
43. 
    Design and implementation of Automatic Test Equipment IP module. [Citation Graph (, )][DBLP]
    
    
44. 
    Add-on blocks and algorithms for improving stimulus compression. [Citation Graph (, )][DBLP]
    
    
45. 
    Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. [Citation Graph (, )][DBLP]
    
    
46. 
    Hybrid test application in hybrid delay scan design. [Citation Graph (, )][DBLP]
    
    
47. 
    Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints. [Citation Graph (, )][DBLP]
    
    
48. 
    Test power reduction in compression-based reconfigurable scan architectures. [Citation Graph (, )][DBLP]
    
    
49. 
    Multivariate model for test response analysis. [Citation Graph (, )][DBLP]
    
    
50. 
    Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. [Citation Graph (, )][DBLP]
    
    
51. 
    Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. [Citation Graph (, )][DBLP]
    
    
52. 
    Algorithm-based fault tolerance for many-core architectures. [Citation Graph (, )][DBLP]
    
    
53. 
    A diagnostic test generation system and a coverage metric. [Citation Graph (, )][DBLP]
    
    
54. 
    A shared BIST optimization methodology for memory test. [Citation Graph (, )][DBLP]
    
    
55. 
    Pipelined parallel test structure for mixed-signal SoCs. [Citation Graph (, )][DBLP]
    
    
56. 
    Setting test conditions for improving SRAM reliability. [Citation Graph (, )][DBLP]
    
    
57. 
    Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. [Citation Graph (, )][DBLP]
    
    
58. 
    Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. [Citation Graph (, )][DBLP]
    
    
59. 
    Test pattern selection to optimize delay test quality with a limited size of test set. [Citation Graph (, )][DBLP]
    
    
60. 
    Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy. [Citation Graph (, )][DBLP]
    
    
61. 
    Current-based testable design of level shifters in liquid crystal display drivers. [Citation Graph (, )][DBLP]
    
    
62. 
    A multi-mode MEMS sensor design to support system test and health & usage monitoring applications. [Citation Graph (, )][DBLP]
    
    
63. 
    A new built-in IDDQ testing method using programmable BICS. [Citation Graph (, )][DBLP]
    
    
64. 
    Defect filter for alternate RF test. [Citation Graph (, )][DBLP]