Conferences in DBLP

Correct Hardware Design and Verification Methods (CHARME) (charme)
1995 (conf/charme/1995)

1. Hardi Hungar, Orna Grumberg, Werner Damm
   What if model checking must be truly symbolic. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:1-20 [Conf]
   
2. Ulrich Stern, David L. Dill
   Automatic verification of the SCI cache coherence protocol. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:21-34 [Conf]
   
3. Laurence Pierre
   Describing and verifying synchronous circuits with the Boyer-Moore theorem prover. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:35-55 [Conf]
   
4. Paul Curzon
   Problems encountered in the machine-assisted proof of hardware. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:56-70 [Conf]
   
5. Dirk Eisenbiegler, Ramayya Kumar
   Formally embedding existing high level synthesis algorithms. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:71-83 [Conf]
   
6. Li-Guo Wang, Michael Mendler
   Formal design of a class of computers. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:84-102 [Conf]
   
7. Michael C. McFarland, Thaddeus J. Kowalski
   Symbolic analysis and verification of CPA descriptions. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:103-123 [Conf]
   
8. Ana Cristina Vieira de Melo, Howard Barringer
   A foundation for formal reuse of hardware. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:124-145 [Conf]
   
9. Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song
   State enumeration with abstract descriptions of state machines. [Citation Graph (0, 0)][DBLP]
   CHARME, 1995, pp:146-160 [Conf]
   
10. Gianpiero Cabodi, Stefano Quer, Paolo Camurati
    Transforming boolean relations by symbolic encoding. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:161-170 [Conf]
    
11. Ayman Wahba, Dominique Borrione
    Design error diagnosis in sequential circuits. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:171-188 [Conf]
    
12. Oded Maler, Amir Pnueli
    Timing analysis of asynchronous circuits using timed automata. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:189-205 [Conf]
    
13. Ulrich Stern, David L. Dill
    Improved probabilistic verification by hash compaction. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:206-224 [Conf]
    
14. Howard Barringer, Graham Gough, Brian Monahan, Alan Williams
    Formal support for the ELLA hardwar description language. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:225-245 [Conf]
    
15. Rocco De Nicola, Alessandro Fantechi, Stefania Gnesi, Salvatore Larosa, Gioia Ristori
    Verifying hardware components within JACK. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:246-260 [Conf]
    
16. Serdar Tasiran, Ramin Hojati, Robert K. Brayton
    Language containment of non-deterministic omega-automata. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:261-277 [Conf]
    
17. Dominique Bolignano
    A partial-order approach to the verification of concurrent systems: checking liveness properties. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:278-292 [Conf]
    
18. David Déharbe, Dominique Borrione
    Semantics of a verification-oriented subset of VHDL. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:293-310 [Conf]
    
19. Kees G. W. Goossens
    Reasoning about VHDL using operational and observational semantics. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:311-327 [Conf]
    
20. Emmanuelle Encrenaz
    A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:328-342 [Conf]