Conferences in DBLP
Viktor Cingel A Graph-Based Method for Timing Diagrams Representation and Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Serafín Olcoz , José Manuel Colom A Petri Net Approach for the Analysis of VHDL Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Alan R. Martello , Steven P. Levitan Temporal Analysis of Time Bounded Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Hanna , Neil Daeche Strongly-Typed Theory of Structures and Behaviours. [Citation Graph (0, 0)][DBLP ] Conf ] Ayman M. Wahba , Einar J. Aas Verification and Diagnosis of Digital Systems by Termary Reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Qinhai Zhang , Charles Trullemans Logic Verification of Incomplete Functions and Design Error Location. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Camurati , Fulvio Corno , Paolo Prinetto A Methodology for System-Level Design for Verifiability. [Citation Graph (0, 0)][DBLP ] Conf ] Neal A. Harman , J. V. Tucker Algebraic Models and the Correctness of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques Chazarain , Hélène Collavizza Combining Symbolic Evaluation and Object-Oriented Approach for Verifying Processor-Like Architectures at the RT-Level. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip J. Windley A Theory of Generic Interpreters. [Citation Graph (0, 0)][DBLP ] Conf ] P. A. Subrahmanyam Towards Verifying Large(r) Systems: A Strategy and an Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati Advancements in Symbolic Traversal Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew M. Bailey Automatic Verification of Speed-Independent Circuit Designs Using the Circal System. [Citation Graph (0, 0)][DBLP ] Conf ] Scott F. Smith , Amy E. Zwarico Correct Compilation of Specifications to Deterministic Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar Bose , Steven D. Johnson DDD-FM9001: Derivation of a Verified Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Joep L. W. Kessels Calculational Derivation of a Counter with Bounded Response Time. [Citation Graph (0, 0)][DBLP ] Conf ] Jifeng He , Ian Page , Jonathan P. Bowen Towards a Provably Correct Hardware Implementation of Occam. [Citation Graph (0, 0)][DBLP ] Conf ] Robin Sharp , Ole Rasmussen Rewriting with Constraints in T-Ruby. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Kropf , Ramayya Kumar , Klaus Schneider Embedding Hardware Verification Within a Commercial Design Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Per Bojsen An Approach to Formalization of Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] 