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Conferences in DBLP

Correct Hardware Design and Verification Methods (CHARME) (charme)
2001 (conf/charme/2001)

  1. Steven D. Johnson
    View from the Fringe of the Fringe. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:1-12 [Conf]
  2. Alan Mycroft, Richard Sharp
    Hardware Synthesis Using SAFL and Application to Processor Design. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:13-39 [Conf]
  3. Robert Beers, Rajnish Ghughal, Mark Aagaard
    Applications of Hierarchical Verification in Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:40-57 [Conf]
  4. Ofer Strichman
    Pruning Techniques for the SAT-Based Bounded Model Checking Problem. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:58-70 [Conf]
  5. M. Oliver Möller, Rajeev Alur
    Heuristics for Hierarchical Partitioning with Application to Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:71-85 [Conf]
  6. Dirk Beyer
    Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:86-91 [Conf]
  7. François Siewe, Dang Van Hung
    Deriving Real-Time Programs from Duration Calculus Specifications. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:92-97 [Conf]
  8. Karen Yorav, Sagi Katz, Ron Kiper
    Reproducing Synchronization Bugs with Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:98-103 [Conf]
  9. Kenneth J. Turner, Ji He
    Formally-Based Design Evaluation. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:104-109 [Conf]
  10. Gérard Berry, Ellen Sentovich
    Multiclock Esterel. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:110-125 [Conf]
  11. Alvin R. Albrecht, Alan J. Hu
    Register Transformations with Multiple Clock Domains. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:126-139 [Conf]
  12. Anthony Winstanley, Mark R. Greenstreet
    Temporal Properties of Self-Timed Rings. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:140-154 [Conf]
  13. Gil Ratzaby, Shmuel Ur, Yaron Wolfsthal
    Coverability Analysis Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:155-160 [Conf]
  14. Ji He, Kenneth J. Turner
    Specifying Hardware Timing with ET-L OTOS. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:161-166 [Conf]
  15. Tiberiu Seceleanu, Juha Plosila
    Formal Pipeline Design. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:167-172 [Conf]
  16. Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri
    Verification of Basic Block Schedules Using RTL Transformations. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:173-178 [Conf]
  17. Kenneth L. McMillan
    Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:179-195 [Conf]
  18. Roope Kaivola, Katherine R. Kohatsu
    Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:196-211 [Conf]
  19. Steve McKeever, Wayne Luk
    Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:212-227 [Conf]
  20. Richard Sharp, Alan Mycroft
    A Higher-Level Language for Hardware Synthesis. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:228-243 [Conf]
  21. Iskander Kort, Sofiène Tahar, Paul Curzon
    Hierarchical Verification Using an MDG-HOL Hybrid Tool. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:244-258 [Conf]
  22. Enrico Tronci, Giuseppe Della Penna, Benedetto Intrigila, Marisa Venturini Zilli
    Exploiting Transition Locality in Automatic Verification. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:259-274 [Conf]
  23. Fady Copty, Amitai Irron, Osnat Weissberg, Nathan P. Kropp, Gila Kamhi
    Efficient Debugging in a Formal Verification Environment. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:275-292 [Conf]
  24. Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Helmut Veith, Dong Wang
    Using Combinatorial Optimization Methods for Quantification Scheduling. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:293-309 [Conf]
  25. Javier Esparza, Claus Schröter
    Net Reductions for LTL Model-Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:310-324 [Conf]
  26. Christoph Berg, Christian Jacobi 0002
    Formal Verification of the VAMP Floating Point Unit. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:325-339 [Conf]
  27. Kanna Shimizu, David L. Dill, Ching-Tsun Chou
    A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® ItaniumTM Processor Bus Protocol. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:340-354 [Conf]
  28. Koen Claessen, Mary Sheeran, Satnam Singh
    The Design and Verification of a Sorter Core. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:355-369 [Conf]
  29. Xiaohua Kong, Radu Negulescu, Larry Weidong Ying
    Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:370-385 [Conf]
  30. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
    Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:386-402 [Conf]
  31. Ricky W. Butler, Victor Carreño, Gilles Dowek, César Muñoz
    Formal Verification of Conflict Detection Algorithms. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:403-417 [Conf]
  32. Eric Gascard, Laurence Pierre
    Induction-Oriented Formal Verification in Symmetric Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:418-432 [Conf]
  33. Mark Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones
    A Framework for Microprocessor Correctness Statements. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:433-448 [Conf]
  34. Huibiao Zhu, Jonathan P. Bowen, Jifeng He
    From Operational Semantics to Denotational Semantics for Verilog. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:449-466 [Conf]
  35. Xuandong Li, Pei Yu, Jianhua Zhao, Yong Li 0005, Tao Zheng, Guoliang Zheng
    Efficient Verification of a Class of Linear Hybrid Automata Using Linear Programming. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:465-480 [Conf]
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