Conferences in DBLP
Wolfram Büttner Is Formal Verification Bound to Remain a Junior Partner of Simulation? [Citation Graph (0, 0)][DBLP ] Conf ] Masaharu Imai , Akira Kitajima Verification Challenges in Configurable Processor Design with ASIP Meister. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas In der Rieden , Dirk Leinenbach , Wolfgang J. Paul Towards the Pervasive Verification of Automotive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Axelsson , Koen Claessen , Mary Sheeran Wired: Wire-Aware Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Warren A. Hunt Jr. , Erik Reeber Formalization of the DE2 Language. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Staber , Barbara Jobstmann , Roderick Bloem Finding and Fixing Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Arindam Chakrabarti , Krishnendu Chatterjee , Thomas A. Henzinger , Orna Kupferman , Rupak Majumdar Verifying Quantitative Properties Using Bound Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Arie Gurfinkel , Marsha Chechik How Thorough Is Thorough Enough? [Citation Graph (0, 0)][DBLP ] Conf ] Liang Zhang , Mukul R. Prasad , Michael S. Hsiao Interleaved Invariant Checking with Dynamic Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. [Citation Graph (0, 0)][DBLP ] Conf ] Viresh Paruthi , Christian Jacobi 0002 , Kai Weber Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. [Citation Graph (0, 0)][DBLP ] Conf ] Orna Grumberg , Tamir Heyman , Nili Ifergan , Assaf Schuster Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Gianfranco Ciardo , Andy Jinqing Yu Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Leslie Lamport Real-Time Model Checking Is Really Simple. [Citation Graph (0, 0)][DBLP ] Conf ] Hana Chockler , Kathi Fisler Temporal Modalities for Concisely Capturing Timing Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Doron Bustan , Alon Flaisher , Orna Grumberg , Orna Kupferman , Moshe Y. Vardi Regular Vacuity. [Citation Graph (0, 0)][DBLP ] Conf ] David Ward , Fabio Somenzi Automatic Generation of Hints for Symbolic Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Baumgartner , Hari Mony Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Jan-Willem Roorda , Koen Claessen A New SAT-Based Algorithm for Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Nina Amla , Xiaoqun Du , Andreas Kuehlmann , Robert P. Kurshan , Kenneth L. McMillan An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Hari Mony , Jason Baumgartner , Adnan Aziz Exploiting Constraints in Transformation-Based Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ou Wei , Arie Gurfinkel , Marsha Chechik Identification and Counter Abstraction for Full Virtual Symmetry. [Citation Graph (0, 0)][DBLP ] Conf ] Iakov Dalinger , Mark A. Hillebrand , Wolfgang J. Paul On the Verification of Memory Management Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhindra Pandav , Konrad Slind , Ganesh Gopalakrishnan Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ritwik Bhattacharya , Steven M. German , Ganesh Gopalakrishnan Symbolic Partial Order Reduction for Rule Based Transition Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Ferdinand , Reinhold Heckmann Verifying Timing Behavior by Abstract Interpretation of Executable Code. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Biniam Gebremichael , Frits W. Vaandrager , Miaomiao Zhang , Kees Goossens , Edwin Rijpkema , Andrei Radulescu Deadlock Prevention in the Æthereal Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Große , Rolf Drechsler Acceleration of SAT-Based Iterative Property Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Subramanian K. Iyer , Jawahar Jain , Mukul R. Prasad , Debashis Sahoo , Thomas Sidle Error Detection Using BMC in a Parallel Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Tsachy Kapschitz , Ran Ginosar Formal Verification of Synchronizers. [Citation Graph (0, 0)][DBLP ] Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva Improvements to the Implementation of Interpolant-Based Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Matousek , Ales Smrcka , Tomás Vojnar High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. [Citation Graph (0, 0)][DBLP ] Conf ] Katell Morin-Allory , David Cachera Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Pell , Wayne Luk Resolving Quartz Overloading. [Citation Graph (0, 0)][DBLP ] Conf ] Mona Safar , M. Watheq El-Kharashi , Ashraf Salem FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Sahoo , Jawahar Jain , Subramanian K. Iyer , David L. Dill , E. Allen Emerson Predictive Reachability Using a Sample-Based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] ShengYu Shen , Ying Qin , Sikun Li Minimizing Counterexample of ACTL Property. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Tsow , Steven D. Johnson Data Refinement for Synchronous System Specification and Construction. [Citation Graph (0, 0)][DBLP ] Conf ] William D. Young Introducing Abstractions via Rewriting. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanuel Zarpas A Case Study: Formal Verification of Processor Critical Properties. [Citation Graph (0, 0)][DBLP ] Conf ] 