Conferences in DBLP
Allan Silburt ASIC/system hardware verification at Nortel: a view from the trenches. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:1- [Conf ] Xiaoshan Li , Antonio Cau , Ben C. Moszkowski , Nick Coleman , Hussein Zedan Proving the correctness of the interlock mechanism in processor design. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:5-22 [Conf ] Werner Damm , Amir Pnueli Verifying out-of-order executions. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:23-47 [Conf ] Ganesh Gopalakrishnan , Rajnish Ghughal , Ravi Hosabettu , Abdelillah Mokkedem , Ratan Nalumasu Formal modeling and validation applied to a commercial coherent bus: a case study. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:48-62 [Conf ] Dominique Borrione , F. Vestman , H. Bouamama An approach to Verilog-VHDL interoperability for synchronous designs. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:65-87 [Conf ] Subash Shankar , James R. Slagle A polymodal semantics for VHDL. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:88-105 [Conf ] Natividad Martínez Madrid , Peter T. Breuer , Carlos Delgado Kloos A semantic model for VHDL-AMS. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:106-123 [Conf ] Carlos M. Roman , Gary De Palma , Robert P. Kurshan Model checking without hardware drivers. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:127- [Conf ] Willem Visser , Howard Barringer , Donal Fellows , Graham Gough , Alan Williams Efficient CTL* model checking for analysis of rainbow designs. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:128-145 [Conf ] Jürgen Ruf , Thomas Kropf Symbolic model checking for a discrete clocked temporal logic with intervals. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:146-163 [Conf ] Gianpiero Cabodi , Paolo Camurati , Antonio Lioy , Massimo Poncino , Stefano Quer A parallel approach to symbolic traversal based on set partitioning. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:167-184 [Conf ] Stefan Höreth Implementation of a multiple-domain decision diagram package. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:185-202 [Conf ] David Déharbe , Anamaria Martins Moreira Using induction and BDDs to model check invariants. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:203-213 [Conf ] Roger B. Hughes CheckOff-M: model checking and its role in IP. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:217- [Conf ] Otmane Aït Mohamed , Xiaoyu Song , Eduard Cerny On the non-termination of MDGs-based abstract state enumeration. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:218-235 [Conf ] Mario Baldi , Fulvio Corno , Maurizio Rebaudengo , Paolo Prinetto , Matteo Sonza Reorda , Giovanni Squillero Simulation-based verification of network protocols performance. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:236-251 [Conf ] Steven D. Johnson , Paul S. Miner Integrated reasoning support in system design: design derivation and theorem proving. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:255-272 [Conf ] George Economakos , George K. Papakonstantinou , Kiamal Z. Pekmestzi , Panayotis Tsanakas Hardware compilation using attribute grammars. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:273-290 [Conf ] Matthias Mutz Automatic post-synthesis verification support for a high level synthesis step by using the HOL theorem proving system. [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:291-308 [Conf ] Carlos M. Roman Is there a crisis in hardware verification? [Citation Graph (0, 0)][DBLP ] CHARME, 1997, pp:309-310 [Conf ]