Conferences in DBLP
(apccas) A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. [Citation Graph (, )][DBLP ] A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs. [Citation Graph (, )][DBLP ] A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs. [Citation Graph (, )][DBLP ] INL Prediction Method in Pipeline ADCs. [Citation Graph (, )][DBLP ] Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOS. [Citation Graph (, )][DBLP ] Improving Source-Follower Buffer for High-Speed ADC Testing. [Citation Graph (, )][DBLP ] 0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application. [Citation Graph (, )][DBLP ] A New Linearity Enhancing Technique for Low Noise Amplifiers. [Citation Graph (, )][DBLP ] A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN. [Citation Graph (, )][DBLP ] 2.4 GHz High IIP3 and Low-Noise Down-conversion Mixer. [Citation Graph (, )][DBLP ] Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs Design. [Citation Graph (, )][DBLP ] An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance. [Citation Graph (, )][DBLP ] Digital Filter Design: Global Solutions via Polynomial Optimization. [Citation Graph (, )][DBLP ] Design of Arbitrary FIR Digital Filters with Group Delay Constraint. [Citation Graph (, )][DBLP ] Symmetry Development for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters. [Citation Graph (, )][DBLP ] A Methodology for Automatic Hardware Synthesis of Multiplier-less Digital Filters with Prescribed Output Accuracy. [Citation Graph (, )][DBLP ] A New Method for Designing Constrained Causal Stable IIR Variable Digital Filters. [Citation Graph (, )][DBLP ] New Structures for Single Filter Based Frequency-Response Masking Approach. [Citation Graph (, )][DBLP ] 3D Shape Acquisition and Arbitrary View Image Generation from Monocular Image Based on Primitive Decomposition. [Citation Graph (, )][DBLP ] Cauchy based Rate-Distortion Optimization Model for H.264 Rate Control. [Citation Graph (, )][DBLP ] A Fast Watermarking System for H.264/AVC Video. [Citation Graph (, )][DBLP ] A New Efficient Approach for Removal of Impulse Noise for Color Images. [Citation Graph (, )][DBLP ] A 0.18µm CMOS Gaussian Monocycle Pulse Circuit Design for UWB. [Citation Graph (, )][DBLP ] VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. [Citation Graph (, )][DBLP ] RaceCheck: A Race Logic Audit Program For SoC Designs. [Citation Graph (, )][DBLP ] A Development and Validation Platform for Communication SOC Design. [Citation Graph (, )][DBLP ] A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. [Citation Graph (, )][DBLP ] Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOC. [Citation Graph (, )][DBLP ] An Adaptive Low-Power Control Scheme for On-Chip Network Applications. [Citation Graph (, )][DBLP ] An Efficient Clocking Scheme for On-Chip Communications. [Citation Graph (, )][DBLP ] Semi-Blind Time Domain Equalization for MIMO-OFDM Systems. [Citation Graph (, )][DBLP ] Linear Precoding For MIMO STC-OFDM And Blind Channel Estimation. [Citation Graph (, )][DBLP ] Multi-degree Random Cyclic Delay Diversity in MISO Systems with Frequency-Domain Scheduling. [Citation Graph (, )][DBLP ] Throughput Maximization in Multiuser MIMO Downlink with Individual QoS Constraints. [Citation Graph (, )][DBLP ] Iterative Symbol-by-symbol Decision Feedback Detection for MIMO-ISI Channels. [Citation Graph (, )][DBLP ] An EM-Based Joint Channel Estimation and Data Detection for SIMO Systems. [Citation Graph (, )][DBLP ] Development of a Wireless Sensor Network System for Power Constrained Applications. [Citation Graph (, )][DBLP ] Design of a Long-Range Wireless Sensor Node. [Citation Graph (, )][DBLP ] Hierarchical Decision-making of Multi-sensor System for State Estimation of Machining Process. [Citation Graph (, )][DBLP ] An Optimized Scheme of Energy Consumption in Wireless Sensor MAC Protocol. [Citation Graph (, )][DBLP ] Noise Analysis and Simulation of Chopper Amplifier. [Citation Graph (, )][DBLP ] A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control. [Citation Graph (, )][DBLP ] Low Power Current-Mode Algorithmic ADC in Half Flash (BCD). [Citation Graph (, )][DBLP ] A Switched-Voltage High-Accuracy Sample/Hold Circuit. [Citation Graph (, )][DBLP ] A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. [Citation Graph (, )][DBLP ] Continuous Time Delta-Sigma Modulators with Arbitrary DAC Waveforms. [Citation Graph (, )][DBLP ] A New Approach for DAC Non-linearity Compensation in Continuous Time Delta Sigma Modulators. [Citation Graph (, )][DBLP ] Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. [Citation Graph (, )][DBLP ] High Power CMOS Power Amplifier for WCDMA. [Citation Graph (, )][DBLP ] A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm. [Citation Graph (, )][DBLP ] A CMOS Digitally Controlled RF Variable Gain Amplifier. [Citation Graph (, )][DBLP ] A 3.125-GHz Limiting Amplifier for Optical Receiver System. [Citation Graph (, )][DBLP ] A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. [Citation Graph (, )][DBLP ] Filterbank Framework for Multicarrier Systems with Improved Subcarrier Separation. [Citation Graph (, )][DBLP ] Performance Analysis of the Deficient Length EDS Adaptive Algorithm. [Citation Graph (, )][DBLP ] An Alternate Approach for Developing Higher Radix FFT Algorithms. [Citation Graph (, )][DBLP ] Signature Verification using Velocity-based Directional Filter Bank. [Citation Graph (, )][DBLP ] Multidimensional Parameters Estimation of Array Signal Based on Steering Vector. [Citation Graph (, )][DBLP ] Wavelet Packet Transform for Scalable Audio Encoder. [Citation Graph (, )][DBLP ] Design of a Low Power Architecture for CABAC Encoder in H.264. [Citation Graph (, )][DBLP ] Frame Based Error Concealment in H.264/AVC by Refined Motion Prediction. [Citation Graph (, )][DBLP ] Matched Block Detection and Motion Vector Salvage Methods for Fast H.264/AVC Inter Mode Decision. [Citation Graph (, )][DBLP ] An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. [Citation Graph (, )][DBLP ] Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding. [Citation Graph (, )][DBLP ] Modified MMSE DMC and Edge Reserving Concealment for Improving H.264 Error Resilience. [Citation Graph (, )][DBLP ] An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity. [Citation Graph (, )][DBLP ] An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform. [Citation Graph (, )][DBLP ] VLSI Realization of Adaptive Equalizers of SIMO FIR Second Order Volterra Channels. [Citation Graph (, )][DBLP ] Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform. [Citation Graph (, )][DBLP ] Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB). [Citation Graph (, )][DBLP ] Adiabatic Smart Card. [Citation Graph (, )][DBLP ] Space-Time Decision-Directed Equalizer for SIMO Systems based on Affine Projection Algorithm. [Citation Graph (, )][DBLP ] A Turbo-BLAST method with Non-Linear MMSE Detector for MIMO-OFDM systems. [Citation Graph (, )][DBLP ] An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction Based on Repeated Utilization of Identical PRSC Sequences in Time Domain. [Citation Graph (, )][DBLP ] Efficient Buffer Management for Retry Mechanism in InfiniBand. [Citation Graph (, )][DBLP ] Enhanced Degree Computationless Modified Euclid's Algorithm. [Citation Graph (, )][DBLP ] A VLSI Design of High Speed Bit-level Viterbi Decoder. [Citation Graph (, )][DBLP ] Global Convergence Analysis of Delayed Bidirectional Associative Memory Neural Networks. [Citation Graph (, )][DBLP ] Using ANN To Predict The Best HUB Location. [Citation Graph (, )][DBLP ] A Generic Architecture for Intelligent System Hardware. [Citation Graph (, )][DBLP ] Recognition of Musical Instruments. [Citation Graph (, )][DBLP ] Pareto based Multi-objective Mapping IP Cores onto NoC Architectures. [Citation Graph (, )][DBLP ] Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules. [Citation Graph (, )][DBLP ] A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems. [Citation Graph (, )][DBLP ] A 4-bit 1.356 Gsps ADC Using Current Processing Method. [Citation Graph (, )][DBLP ] A 6-bit 2.704Gsps DAC for DS-CDMA UWB. [Citation Graph (, )][DBLP ] A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter. [Citation Graph (, )][DBLP ] An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN. [Citation Graph (, )][DBLP ] A 0.18µm CMOS Fully Differential RF Demodulator for FM-UWB Based P-PAN Receivers. [Citation Graph (, )][DBLP ] A 0.18-µm CMOS UWB Low Noise Amplifier for Full-Band (3.1-10.6GHz) Application. [Citation Graph (, )][DBLP ] 3~5 GHz Cascoded UWB Power Amplifier. [Citation Graph (, )][DBLP ] A Fully Integrated 3 to 5 GHz CMOS Mixer with Active Balun for UWB Receiver. [Citation Graph (, )][DBLP ] A Novel FFT Processor for OFDM UWB Systems. [Citation Graph (, )][DBLP ] Design of Optimal Decimation and Interpolation Filters for Low Bit-Rate Image Coding. [Citation Graph (, )][DBLP ] Multiple Description Image Coding With Hybrid Redundancy. [Citation Graph (, )][DBLP ] Image Enhancement Algorithm for Hexagonal Cellular Neural Networks. [Citation Graph (, )][DBLP ] Minimization of L2-Sensitivity for 2-D Separable-Denominator State-Space Digital Filters Subject to L2-Scaling Constraints. [Citation Graph (, )][DBLP ] Design of Delta Operator Based 2-D IIR Filters Using Symmetrical Decomposition. [Citation Graph (, )][DBLP ] A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. [Citation Graph (, )][DBLP ] Unequal-arm Adaptive Rood Pattern Search with Early Terminations For Fast Block-matching Motion Estimation on H.264. [Citation Graph (, )][DBLP ] Motion Vector Estimation and Adatptive Refinement for the MPEG-4 to H.264/AVC Video Transcoder. [Citation Graph (, )][DBLP ] Exploiting Reference Frame History in H.264/AVC Motion Estimation. [Citation Graph (, )][DBLP ] Fast Motion Estimation Algorithm by Finite-State Side Match for H.264 Video Coding Standard. [Citation Graph (, )][DBLP ] Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures. [Citation Graph (, )][DBLP ] Redundant Adders Consume Less Energy. [Citation Graph (, )][DBLP ] A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. [Citation Graph (, )][DBLP ] Design of Clocked Transmission Gate Adiabatic Logic Circuit Based on the 3ECEAC. [Citation Graph (, )][DBLP ] A New Class AB Current-Mode Circuit for Low-Voltage Applications. [Citation Graph (, )][DBLP ] A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences. [Citation Graph (, )][DBLP ] A Resolution- and Rate- Scalable Image Subband Coding Scheme with Backward Coding of Wavelet Trees. [Citation Graph (, )][DBLP ] Design of Time Domain Equalizers Incorporating Radio Frequency Interference Suppression. [Citation Graph (, )][DBLP ] Flexible Filter Bank Dimensioning for Multicarrier Modulation and Frequency Domain Equalization. [Citation Graph (, )][DBLP ] Prototype Filter Design for a Cosine-Modulated Filterbank Transmultiplexer. [Citation Graph (, )][DBLP ] VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. [Citation Graph (, )][DBLP ] Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. [Citation Graph (, )][DBLP ] DCT Sign Only Correlation and Its Application to Image Registration. [Citation Graph (, )][DBLP ] Image Registration using Fractional Fourier Transform. [Citation Graph (, )][DBLP ] Design of an Area Efficient High-Speed Color FDWT Processor. [Citation Graph (, )][DBLP ] System Design of Implantable Micro-stimulator for Medical Treatments. [Citation Graph (, )][DBLP ] A Wide-Range and High PSRR CMOS Voltage Reference for Implantable Device. [Citation Graph (, )][DBLP ] Some Recent Developments in the Design of Biopotential Amplifiers for ENG Recording Systems. [Citation Graph (, )][DBLP ] A Micropower CMOS Amplifier for Portable Surface EMG Recording. [Citation Graph (, )][DBLP ] Low Power SAW-Based Oscillator for an Implantable Multisensor Microsystem. [Citation Graph (, )][DBLP ] A Miniaturized, Power-Efficent Stimulator Output Stage Based on the Bridge Rectifier Circuit. [Citation Graph (, )][DBLP ] A Low-Power Low-Voltage Amplifier for Heart Rate Sensor. [Citation Graph (, )][DBLP ] Design of 3-4GHz Tunable Low Noise LC-QVCO for IEEE 802.11a WLAN Application. [Citation Graph (, )][DBLP ] A 6.5-GHz LC VCO with Integrated-Transformer Tuning. [Citation Graph (, )][DBLP ] A CMOS Dual-Band Voltage Controlled Oscillator. [Citation Graph (, )][DBLP ] A Low-Voltage 2.4GHz VCO with 3D Helical Inductors. [Citation Graph (, )][DBLP ] 0.8 V GPS band CMOS VCO with 29% Tuning Range. [Citation Graph (, )][DBLP ] A Novel 16-bit CMOS Digitally Controlled Oscillator. [Citation Graph (, )][DBLP ] A Wide Input-Range Sigma Delta Modulator for Applications to Spread-Spectrum Clock Generator. [Citation Graph (, )][DBLP ] Bit-Serial Digital Filter Implementation using a Custom C Compiler. [Citation Graph (, )][DBLP ] Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous Systems. [Citation Graph (, )][DBLP ] FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters. [Citation Graph (, )][DBLP ] Broadband Beamforming of Bandpass Plane Waves using 2D FIR Trapezoidal Filters at Baseband. [Citation Graph (, )][DBLP ] Efficient Implementation of the Fast Filter Bank For Critically Decimated Systems. [Citation Graph (, )][DBLP ] Optimized Design of Extrapolated Impulse Response FIR Filters with Raised-Cosine Windows. [Citation Graph (, )][DBLP ] A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. [Citation Graph (, )][DBLP ] Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor. [Citation Graph (, )][DBLP ] Implementation of a H.264 decoder with Template-based Communication Refinement. [Citation Graph (, )][DBLP ] Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding. [Citation Graph (, )][DBLP ] Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC. [Citation Graph (, )][DBLP ] An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications. [Citation Graph (, )][DBLP ] High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding. [Citation Graph (, )][DBLP ] Asynchronous Design Methodology for an Efficient Implementation of Low power ALU. [Citation Graph (, )][DBLP ] Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. [Citation Graph (, )][DBLP ] A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques. [Citation Graph (, )][DBLP ] Low Power Multiplier with Bypassing and Tree Strucuture. [Citation Graph (, )][DBLP ] Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation. [Citation Graph (, )][DBLP ] New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm. [Citation Graph (, )][DBLP ] High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. [Citation Graph (, )][DBLP ] Advances in Global Optimization: Novel Function Transformation Approaches. [Citation Graph (, )][DBLP ] A Filled Function Method for Box-constrained System of Nonlinear Equations. [Citation Graph (, )][DBLP ] An Optimization Problem on Two-Partition of Jobs for Profit Allocation. [Citation Graph (, )][DBLP ] A Recursive Digital Filter Design using Global Optimization Technique. [Citation Graph (, )][DBLP ] Linear Incentive Contract for Principal-agent Problem with Asymmetric Information and Moral Hazard. [Citation Graph (, )][DBLP ] Results on Exactness Properties of the HP-ALF for Inequality Constraints. [Citation Graph (, )][DBLP ] A Total Unimodularity Based Branch-and-Bound Method for Integer Programming. [Citation Graph (, )][DBLP ] Hybrid Dual-Operating-Mode PWM Based Sliding Mode Controllers for DC-DC Converters. [Citation Graph (, )][DBLP ] Practical Implementation of Sliding Mode Control for Boost Converter. [Citation Graph (, )][DBLP ] Current-Mode Converters with Adjustable-Slope Compensating Ramp. [Citation Graph (, )][DBLP ] Steady-State Performance Analysis of Cascade Boost Converters. [Citation Graph (, )][DBLP ] A Monolithic Boost Converter with an Adaptable Current-Limited PFM Scheme. [Citation Graph (, )][DBLP ] On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. [Citation Graph (, )][DBLP ] Embedded DC-DC Voltage Down Converter for Low-Power VLSI Chip. [Citation Graph (, )][DBLP ] Design of a Wireless Power Supply Receiver for Biomedical Applications. [Citation Graph (, )][DBLP ] A Novel DPWM Based on Fully Table Look-Up for High-Frequency Power Conversion. [Citation Graph (, )][DBLP ] An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. [Citation Graph (, )][DBLP ] A Novel Current Feed-back Sub-Nano-Siemen Transconductance Circuit Suitable for Large Time-Constant Bio-medical Applications. [Citation Graph (, )][DBLP ] Design of Low-Frequency Low-Pass Filters for Biomedical Applications. [Citation Graph (, )][DBLP ] A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing. [Citation Graph (, )][DBLP ] Parallel Discovery of Transcription Factor Binding Sites. [Citation Graph (, )][DBLP ] Low Power Bootstrapped CMOS Differential Cross Coupled Driver. [Citation Graph (, )][DBLP ] A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. [Citation Graph (, )][DBLP ] Two Novel Phase-Frequency Detectors. [Citation Graph (, )][DBLP ] Detailed Behavioral Modeling of Bang-Bang Phase Detectors. [Citation Graph (, )][DBLP ] Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D Amplifiers. [Citation Graph (, )][DBLP ] An Analysis of THD in Class D Amplifiers. [Citation Graph (, )][DBLP ] A BiCMOS Low Voltage Low Distortion Class AB Amplifier. [Citation Graph (, )][DBLP ] A Genetic Algorithm Employing Correlative Roulette Selection for Optimization of FRM Digital Filters over CSD Multiplier Coefficient Space. [Citation Graph (, )][DBLP ] Frequency-Response Masking Approach for Design of Intermediate Frequency Filters in CDMA and Wideband GSM Modules. [Citation Graph (, )][DBLP ] On the Use of Lyapunov Functions for the Design of Complex FIR Digital Filters. [Citation Graph (, )][DBLP ] An Algorithm for the Design of Multiplierless IIR Filters as a Parallel Connection of Two All-Pass Filters. [Citation Graph (, )][DBLP ] Mitigation of Narrowband Interference in SC Transmission with Filter Bank Equalization. [Citation Graph (, )][DBLP ] Theory, Lattice Structure and Design of Unequal Length Linear Phase Perfect Reconstruction Filter Banks with More Flexible Length Profile. [Citation Graph (, )][DBLP ] Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. [Citation Graph (, )][DBLP ] A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile. [Citation Graph (, )][DBLP ] Predictive Mode Searching Policy for H.264/AVC Intra Prediction. [Citation Graph (, )][DBLP ] Fast Picture and Macroblock Level Adaptive Frame/Field Coding for H.264. [Citation Graph (, )][DBLP ] A Fast Macroblock Mode Decision Algorithm for H.264. [Citation Graph (, )][DBLP ] Cost-Effective Hardware Sharing Architectures of Fast 8×8 and 4×4 Integer Transforms for H.264/AVC. [Citation Graph (, )][DBLP ] New Encoding of 8×8 DCT to make H.264 Lossless. [Citation Graph (, )][DBLP ] A Convex Optimization-Based Object-Level Rate Control Algorithm for MPEG-4 Video Object Coding. [Citation Graph (, )][DBLP ] A Certain SA Solver TOSA for Global Placement. [Citation Graph (, )][DBLP ] A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. [Citation Graph (, )][DBLP ] Design Partitioning for Reducing Crosstalk Analysis Time. [Citation Graph (, )][DBLP ] Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. [Citation Graph (, )][DBLP ] Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint! [Citation Graph (, )][DBLP ] Post-placement Thermal Via Planning for 3D Integrated Circuit. [Citation Graph (, )][DBLP ] Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. [Citation Graph (, )][DBLP ] Uniform DFT Filter Bank with Finite Precision Prototype Filters. [Citation Graph (, )][DBLP ] Fourth-Order Discrete-Time Variable Centre Frequency Bandpass Sigma-Delta Modulator. [Citation Graph (, )][DBLP ] Post-Filtering Techniques For Directive Non-Stationary Source Combined With Stationary Noise Utilizing Spatial Spectral Processing. [Citation Graph (, )][DBLP ] Blind Subband Beamforming for Speech Enhancement of Multiple Speakers. [Citation Graph (, )][DBLP ] An Optimisation Approach to Robust Estimation of Multicomponent Polynomial Phase Signals in Non-Gaussian Noise. [Citation Graph (, )][DBLP ] Exploiting Concurrency in System-on-Chip Verification. [Citation Graph (, )][DBLP ] Bistatic Ambiguity Function and DOA Estimation for PCL Radar. [Citation Graph (, )][DBLP ] Single DC/AC CCFL Inverter for Large Size LCD TV with Burst Control. [Citation Graph (, )][DBLP ] Fuzzy-based Active and Reactive Control for Brushless Doubly-fed Wind Power Generation System. [Citation Graph (, )][DBLP ] Effects of PV Grid-Connected System Location on a Distribution System. [Citation Graph (, )][DBLP ] The Calculation of the Voltage Distribution in Transformer Windings under VFTO Based on FDTD Method. [Citation Graph (, )][DBLP ] A High Frequency Circuit Model for Current Transformer Based on the Scattering Parameter. [Citation Graph (, )][DBLP ] High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. [Citation Graph (, )][DBLP ] Peak Power Minimization through Power Management Scheduling. [Citation Graph (, )][DBLP ] Development of a CMOS Imaging Device for Functional Imaging Inside the Mouse Brain. [Citation Graph (, )][DBLP ] Stability and Compensation Technique for a CMOS Amperometric Potentiostat Circuit for Redox Sensors. [Citation Graph (, )][DBLP ] A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. [Citation Graph (, )][DBLP ] Endothelial Cell Image Enhancement using Decimation-Free Directional Filter Banks. [Citation Graph (, )][DBLP ] Testing the Quality of Magnetic Gradient Fields for Studying Self-Diffusion Processes in Biological Specimens by Magnetic Resonance Methods. [Citation Graph (, )][DBLP ] Current-mode Universal Filter with Four Inputs and One Output using CDTAs. [Citation Graph (, )][DBLP ] Current-mode Active-only Universal Filter. [Citation Graph (, )][DBLP ] Independent Tunable-Q Current-mode OTA-C Universal Filter. [Citation Graph (, )][DBLP ] Oscillation-based Test Method for Continuous-time OTA-C Filters. [Citation Graph (, )][DBLP ] Synthesis of Delay Equalized Time-Varying Butterworth Filters. [Citation Graph (, )][DBLP ] Multirate Filters: An Overview. [Citation Graph (, )][DBLP ] Stepped Triangular CIC Filter for Rational Sample Rate Conversion. [Citation Graph (, )][DBLP ] A Novel Systematic Approach for Synthesizing Multiplication-Free Highly-Selective FIR Half-Band Decimators and Interpolators. [Citation Graph (, )][DBLP ] Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques. [Citation Graph (, )][DBLP ] On the Design of Cosine-Modulated Filter Banks Using Recurrent Frequency-Response Masking. [Citation Graph (, )][DBLP ] The Dyadic Curvelet Transform for Multiscale Topological Complex Networks. [Citation Graph (, )][DBLP ] Subword Parallel Architecture for Connected Component Labeling and Morphological Operations. [Citation Graph (, )][DBLP ] Markov Chain Monte Carlo Super-resolution Image Reconstruction With Artifacts Suppression. [Citation Graph (, )][DBLP ] An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. [Citation Graph (, )][DBLP ] A One-Dimensional Technique for Embedding Data in A JPEG Color Image. [Citation Graph (, )][DBLP ] Techniques of Power-gating to Kill Sub-Threshold Leakage. [Citation Graph (, )][DBLP ] Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET. [Citation Graph (, )][DBLP ] Leakage Optimized DECAP Design for FPGAs. [Citation Graph (, )][DBLP ] Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate. [Citation Graph (, )][DBLP ] A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection. [Citation Graph (, )][DBLP ] Jointly Optimized Modulated-Transmitter and Receiver FIR MIMO Filters. [Citation Graph (, )][DBLP ] Comparison of Filter Bank Based Multicarrier Systems with OFDM. [Citation Graph (, )][DBLP ] Nonlinear and Decision-Oriented Signal Processing for OFDM-Based Wireless Communications. [Citation Graph (, )][DBLP ] A Real-Time Digital Baseband Channel Emulation System for OFDM Communications. [Citation Graph (, )][DBLP ] Synchronization Issues in OFDM Systems. [Citation Graph (, )][DBLP ] Footstep Recognition with Psyco-acoustics Parameter. [Citation Graph (, )][DBLP ] A Robust Anti-collusion Coding in Digital Fingerprinting System. [Citation Graph (, )][DBLP ] Automatic Detection and Segmentation of Text in Low Quality Thai Sign Images. [Citation Graph (, )][DBLP ] Real-Time Implementation of a Particle Filter with Integrated Voice Activity Detector for Acoustic Speaker Tracking. [Citation Graph (, )][DBLP ] Early Detection on the Condition of Pancreas Organ as the Cause of Diabetes Mellitus by Real Time Iris Image Processing. [Citation Graph (, )][DBLP ] On Finding a Solution in the Core of a Multicommodity Flow Game on a Spider. [Citation Graph (, )][DBLP ] Sequence-Pair Based Compaction under Equi-Length Constraint. [Citation Graph (, )][DBLP ] Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament. [Citation Graph (, )][DBLP ] Kernel Extraction for Watermarking Combinational Logic Networks. [Citation Graph (, )][DBLP ] Wavelet Packet Decomposition-Based Fuzzy Clustering Algorithm for Gene Expression Data. [Citation Graph (, )][DBLP ] An Active-RC Complex Filter with Mixed Signal Tuning System for Low-IF Receiver. [Citation Graph (, )][DBLP ] Generalized Bandpass Sampling with Complex FIR Filtering. [Citation Graph (, )][DBLP ] A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications. [Citation Graph (, )][DBLP ] The Analysis of Phase-jitter Variance in the Third-order CPPLL Frequency Synthesizer. [Citation Graph (, )][DBLP ] An Efficient Realization of the Decision Feedback Equalizer using Block Floating Point Arithmetic. [Citation Graph (, )][DBLP ] Frequency Transformations of IIR Filters with Filter Bank Applications. [Citation Graph (, )][DBLP ] Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques. [Citation Graph (, )][DBLP ] Parallelisation of Digital Signal Processing in Uniform and Reconfigurable Filter Banks for Satellite Communications. [Citation Graph (, )][DBLP ] Design of Real and Complex Linear-Phase IIR Modified QMF Banks. [Citation Graph (, )][DBLP ] A Determination Method for Initial Values of Coplanar Camera Calibration Parameters. [Citation Graph (, )][DBLP ] Implementation of an AMBA-Compliant IP for H.264 Transform and Quantization. [Citation Graph (, )][DBLP ] VSIP : Implementation of Video Specific Instruction-set Processor. [Citation Graph (, )][DBLP ] An Implementation of H.264 Intra Predictor Based on Sub-sampling. [Citation Graph (, )][DBLP ] SoC Design of Speaker Connection System by Efficient Cosimulation. [Citation Graph (, )][DBLP ] On the Configurable Multiprocessor SoC Platform with Crossbar Switch. [Citation Graph (, )][DBLP ] DFM-aware Routing for Yield Enhancement. [Citation Graph (, )][DBLP ] A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. [Citation Graph (, )][DBLP ] Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation. [Citation Graph (, )][DBLP ] A Hitchhiker's Guide to the DFM Universe. [Citation Graph (, )][DBLP ] Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach. [Citation Graph (, )][DBLP ] A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers. [Citation Graph (, )][DBLP ] Pipelined Parallel Architectures for High Throughput Turbo Decoding. [Citation Graph (, )][DBLP ] Linear Adaptive Blind Equalizers of Non Linear SIMO FIR Channels. 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