Conferences in DBLP
Gérard Berry Esterel and Jazz: Two Synchronous Languages for Circuit Design (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Peter Jansen Design Process of Embedded Automotive Systems - Using Model Checking for Correct Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Hosabettu , Ganesh Gopalakrishnan , Mandayam K. Srivas A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Cook , John Launchbury , John Matthews , Richard B. Kieburtz Formal Verification of Explicitly Parallel Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev , Randal E. Bryant Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Yu , Panagiotis Manolios , Leslie Lamport Model Checking TLA+ Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Nina Amla , E. Allen Emerson , Kedar S. Namjoshi Efficient Decompositional Model Checking for Regular Timing Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Orna Kupferman , Moshe Y. Vardi Vacuity Detection in Temporal Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Cindy Eisner Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Xu , Eduard Cerny , Allan Silburt , A. Coady , Ying Liu , Philip Pownall Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors. [Citation Graph (0, 0)][DBLP ] Conf ] Marius Bozga , Oded Maler , Stavros Tripakis Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics. [Citation Graph (0, 0)][DBLP ] Conf ] E. Allen Emerson , Richard J. Trefler From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk W. Hoffmann , Thomas Kropf Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Somesh Jha , Yuan Lu , Dong Wang Abstract BDDs: A Technque for Using Abstraction in Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Blumenröhr , Viktor K. Sabelfeld Formal Synthesis at the Algorithmic Level. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Aagaard , Thomas F. Melham , John W. O'Leary Xs are for Trajectory Evaluation, Booleans are for Theorem Proving. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. McMillan Verification of Infinite State Systems by Compositional Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gerd Ritter , Hans Eveking , Holger Hinrichsen Formal Verification of Designs with Complex Control by Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kavita Ravi , Fabio Somenzi Hints to accelerate Symbolic Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Ruf , Thomas Kropf Modleing and Checking Networks of Communicating Real-Time Process. [Citation Graph (0, 0)][DBLP ] Conf ] Sagi Katz , Orna Grumberg , Daniel Geist "Have I written enough Properties?" - A Method of Comparison between Specification and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Masahiro Fujita , Sreeranga P. Rajan , Thomas W. Reps , Subash Shankar , Tim Teitelbaum Program Slicing of Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Sawada , Warren A. Hunt Jr. Results of the Verification of a Complex Pipelined Machine Model. [Citation Graph (0, 0)][DBLP ] Conf ] Hüsnü Yenigün , Vladimir Levin , Doron Peled , Peter A. Beerel Hazard-Freedom Checking in Speed-Independent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider Yet another Look at the LTL Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Hendricx , Luc J. M. Claesen Verification of Finite-State-Machine Refinements Using a Symbolic Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] George Economakos , George K. Papakonstantinou Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. [Citation Graph (0, 0)][DBLP ] Conf ] Steven D. Johnson , Yanhong A. Liu , Yuchen Zhang A Systematic Incrementalization Technique and Its Application to Hardware Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kathi Fisler , Moshe Y. Vardi Bisimulation and Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. McMillan Circular Compositional Reasoning about Liveness. [Citation Graph (0, 0)][DBLP ] Conf ] Nancy A. Day , Jeffrey R. Lewis , Byron Cook Symbolic Simulation of Microprocessor Models using Type Classes in Haskell. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Pranav Ashar , Sharad Malik Exploiting Retiming in a Guided Simulation Based Validation Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Chr. Godesken Fault Models for Embedded Systems (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider , Michaela Huhn , George Logothetis Validation of Object-Oriented Concurrent Designs by Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] 