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Conferences in DBLP

Computer Hardware Description Languages and their Applications (chdl)
1993 (conf/chdl/1993)

  1. Mario Barbacci
    Real Time Distributed Systems. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:3-12 [Conf]
  2. Edmund M. Clarke, Orna Grumberg, Hiromi Hiraishi, Somesh Jha, David E. Long, Kenneth L. McMillan, Linda A. Ness
    Verification of the Futurebus+ Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:15-30 [Conf]
  3. Paolo Camurati, Fulvio Corno, Paolo Prinetto
    Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:31-44 [Conf]
  4. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Hardware-Verification using First Order BDDs. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:45-62 [Conf]
  5. Klaus Buchenrieder, Alexander Sedlmeier, Christian Veith
    HW/SW Co-Design with PRAMs Using CoDES. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:65-78 [Conf]
  6. Flávio Rech Wagner
    Prevail-DM: A Framework-Based Environment for Formal Hardware Verification. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:79-96 [Conf]
  7. C. Norris Ip, David L. Dill
    Better Verification Through Symmetry. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:97-111 [Conf]
  8. Michel Allemand
    A Rewriting Based Method for the Formal Verification of Microprocessors. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:115-122 [Conf]
  9. J. W. Gambles, Phillip J. Windley
    Reasoning about the VHDL Standard Logic Package Signal Data Type. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:123-130 [Conf]
  10. Xing-Jian Xu, Mitsuru Ishizuka
    An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:131-138 [Conf]
  11. Bhaskar Bose, Steven D. Johnson, Shyamsundar Pullela
    Integrating Boolean Verification with Formal Derivation. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:139-146 [Conf]
  12. Francisco Corella
    Automated High-level Verification Against Clocked Algorithmic Specifications. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:147-154 [Conf]
  13. Stefan Krischer
    The Backward Walk Approach in FSM Verification. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:155-162 [Conf]
  14. Edmund M. Clarke
    Automatic Verification of Sequential Circuit Designs. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:165- [Conf]
  15. Kamlesh Rath, Steven D. Johnson
    Toward a Basis for Protocol Specification and Process Decomposition. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:169-186 [Conf]
  16. Wolfgang Glunz, Thomas Kruse, Torsten Rössel, Dieter Monjau
    Integrating SDL and VHDL for System-Level Hardware Design. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:187-204 [Conf]
  17. Alan Dent, Keith Hanna
    Reasoning about Array Structure Using a Dependently Typed Logic. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:207-224 [Conf]
  18. Laurence Pierre
    VHDL Description and Formal Verification of Systolic Multipliers. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:225-242 [Conf]
  19. Robin Sharp, Ole Rasmussen
    Transformational Rewriting with Ruby. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:243-260 [Conf]
  20. Roger P. Ang, Nikil D. Dutt
    A Representation for the Binding of RT-Component Functionality to HDL Behavior. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:263-280 [Conf]
  21. Ram Mandayam, Ranga Vemuri
    Performance Specification and Measurement. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:281-298 [Conf]
  22. Zheng Zhu, Steven D. Johnson
    Automatic Synthesis of Sequential Synchronizations. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:299-315 [Conf]
  23. Mohammed Faci, Luigi Logrippo
    Specifying Hardware Systems in LOTOS. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:319-326 [Conf]
  24. John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard
    HML: A Hardware Description Language Based on Standard ML. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:327-334 [Conf]
  25. Bran Selic
    An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:335-344 [Conf]
  26. Ahmed Amine Jerraya, Kevin O'Brien, Tarek Ben Ismail
    Linking System Design Tools and Hardware Design Tools. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:345-351 [Conf]
  27. Sungho Kang, Stephen A. Szygenda
    Automatic VHDL Model Generation System. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:353-360 [Conf]
  28. Balraj Singh, John Wicks, Philip Wright, James R. Armstrong
    The Modeler's Assistant: A CAD Tool for Behavioral Model Development. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:361-368 [Conf]
  29. Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar
    Insulin: An Instruction Set Simulation Environment. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:369-376 [Conf]
  30. Gregor von Bochmann
    Specification Languages for Communication Protocols. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:379-396 [Conf]
  31. Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt
    Integrating Behavior and Timing in Executable Specifications. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:399-416 [Conf]
  32. Tam Anh Chu, Huy T. Cao, Clement K. C. Leung
    ESP: An Executable Specification Language for Mixed Timing Control Circuits. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:417-434 [Conf]
  33. Tamio Hoshino
    UDL/I version Two: A New Horizon of HDL Standards. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:437-452 [Conf]
  34. Felice Balarin, Gary York
    Verilog HDL Modeling Styles for Formal Verification. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:453-465 [Conf]
  35. Eric J. Golin, Annette C. Feng
    A Visual Hardware Description Language. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:467-484 [Conf]
  36. Walling R. Cyre
    Textual/Graphical Design Concept-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:485-502 [Conf]
  37. Wolfgang Ecker, Sabine März
    System-Level Specification and Design Using VHDL: A Case Study. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:505-522 [Conf]
  38. Karen C. Davis
    A Denotational Definition of the VHDL Simulation Kernel. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:523-535 [Conf]
  39. Wolfgang Glunz, Torsten Rössel
    Checking DFT Rules with a VHDL Simulator. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:537-550 [Conf]
  40. Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen
    Parameterized VHDL Entities for the Simulation of Hybrid Circuits. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:551-567 [Conf]
  41. Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai
    Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:569-586 [Conf]
  42. Dominique Rodriguez
    Analog-VHDL: As an Application, a Real Example. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:587-604 [Conf]
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