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Conferences in DBLP

Cryptographic Hardware and Embedded Systems (CHES) (ches)
2005 (conf/ches/2005)

  1. William Dupuy, Sébastien Kunz-Jacques
    Resistance of Randomized Projective Coordinates Against Power Analysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:1-14 [Conf]
  2. Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm
    Templates as Master Keys. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:15-29 [Conf]
  3. Werner Schindler, Kerstin Lemke, Christof Paar
    A Stochastic Model for Differential Side Channel Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:30-46 [Conf]
  4. Jean-Sébastien Coron, David Lefranc, Guillaume Poupard
    A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:47-60 [Conf]
  5. P. J. Green, Richard Noad, Nigel P. Smart
    Further Hidden Markov Model Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:61-74 [Conf]
  6. Johann Großschädl, Roberto Maria Avanzi, Erkay Savas, Stefan Tillich
    Energy-Efficient Software Implementation of Long Integer Modular Arithmetic. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:75-90 [Conf]
  7. Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume
    Short Memory Scalar Multiplication on Koblitz Curves. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:91-105 [Conf]
  8. Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede
    Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:106-118 [Conf]
  9. Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke
    SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:119-130 [Conf]
  10. Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer
    Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:131-146 [Conf]
  11. Marco Bucci, Raimondo Luzzi
    Design of Testable Random Bit Generators. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:147-156 [Conf]
  12. Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald
    Successfully Attacking Masked AES Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:157-171 [Conf]
  13. Thomas Popp, Stefan Mangard
    Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:172-186 [Conf]
  14. Wieland Fischer, Berndt M. Gammel
    Masking at Gate Level in the Presence of Glitches. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:187-200 [Conf]
  15. Marcelo E. Kaihara, Naofumi Takagi
    Bipartite Modular Multiplication. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:201-210 [Conf]
  16. Laszlo Hars
    Fast Truncated Multiplication for Cryptographic Applications. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:211-225 [Conf]
  17. Martin Seysen
    Using an RSA Accelerator for Modular Inversion. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:226-236 [Conf]
  18. Berk Sunar, David Cyganski
    Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:237-249 [Conf]
  19. Catherine H. Gebotys, Simon Ho, C. C. Tiu
    EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:250-264 [Conf]
  20. Markus G. Kuhn
    Security Limits for Compromising Emanations. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:265-279 [Conf]
  21. Huiyun Li, A. Theodore Markettos, Simon W. Moore
    Security Evaluation Against Electromagnetic Analysis at Design Time. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:280-292 [Conf]
  22. Marc Joye, Pascal Paillier, Berry Schoenmakers
    On Second-Order Differential Power Analysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:293-308 [Conf]
  23. Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater
    Improved Higher-Order Side-Channel Attacks with FPGA Experiments. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:309-323 [Conf]
  24. Ulrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble
    Secure Data Management in Trusted Computing. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:324-338 [Conf]
  25. Sergei P. Skorobogatov
    Data Remanence in Flash Memory Devices. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:339-353 [Conf]
  26. Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:354-365 [Conf]
  27. Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
    DPA Leakage Models for CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:366-382 [Conf]
  28. Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
    The "Backend Duplication" Method. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:383-397 [Conf]
  29. Philipp Grabher, Dan Page
    Hardware Acceleration of the Tate Pairing in Characteristic Three. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:398-411 [Conf]
  30. Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto
    Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:412-426 [Conf]
  31. Tim Good, Mohammed Benaissa
    AES on FPGA from the Fastest to the Smallest. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:427-440 [Conf]
  32. David Canright
    A Very Compact S-Box for AES. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:441-455 [Conf]
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