Conferences in DBLP
Darrel Hankerson , Julio López Hernandez , Alfred Menezes Software Implementation of Elliptic Curve Cryptography over Binary Fields. [Citation Graph (0, 0)][DBLP ] Conf ] Souichi Okada , Naoya Torii , Kouichi Itoh , Masahiko Takenaka Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m ) on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Gerardo Orlando , Christof Paar A High Performance Reconfigurable Elliptic Curve Processor for GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Jae Wook Chung , Sang Gyoo Sim , Pil Joong Lee Fast Implementation of Elliptic Curve Defined over GF(p m ) on CalmRISC with MAC2424 Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Adi Shamir Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies. [Citation Graph (0, 0)][DBLP ] Conf ] Rita Mayer-Sommer Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards. [Citation Graph (0, 0)][DBLP ] Conf ] M. Anwarul Hasan Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems. [Citation Graph (0, 0)][DBLP ] Conf ] Werner Schindler A Timing Attack against RSA with the Chinese Remainder Theorem. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Dandalis , Viktor K. Prasanna , José D. P. Rolim A Comparative Study of Performance of AES Final Candidates Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Cameron Patterson A Dynamic FPGA Implementation of the Serpent Block Cipher. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Trimberger , Raymond Pang , Amit Singh A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Herbert Leitold , Wolfgang Mayerwieser , Udo Payer , Karl C. Posch , Reinhard Posch , Johannes Wolkerstorfer A 155 Mbps Triple-DES Network Encryptor. [Citation Graph (0, 0)][DBLP ] Conf ] James Goodman , Anantha Chandrakasan An Energy Efficient Reconfigurable Public-Key Cryptograhpy Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Johann Großschädl High-Speed RSA Hardware Based on Barret's Modular Reduction Method. [Citation Graph (0, 0)][DBLP ] Conf ] Colin D. Walter Data Integrity in Hardware for Modular Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Takehiko Kato , Satoru Ito , Jun Anzai , Natsume Matsuzaki A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals. [Citation Graph (0, 0)][DBLP ] Conf ] David Naccache , Michael Tunstall How to Explain Side-Channel Leakage to Your Kids. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Sébastien Coron , Louis Goubin On Boolean and Arithmetic Masking against Differential Power Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas S. Messerges Using Second-Order Power Analysis to Attack DPA Resistant Software. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Clavier , Jean-Sébastien Coron , Nora Dabbous Differential Power Analysis in the Presence of Hardware Countermeasures. [Citation Graph (0, 0)][DBLP ] Conf ] Huapeng Wu Montgomery Multiplier and Squarer in GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Erkay Savas , Alexandre F. Tenca , Çetin Kaya Koç A Scalable and Unified Multiplier Architecture for Finite Fields GF(p ) and GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Gaël Hachez , Jean-Jacques Quisquater Montgomery Exponentiation with no Final Subtractions: Improved Results. [Citation Graph (0, 0)][DBLP ] Conf ] Steve H. Weingart Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defences. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Pornin , Jacques Stern Software-Hardware Trade-Offs: Application to A5/1 Cryptanalysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Hoffstein , Joseph H. Silverman MiniPASS: Authentication and Digital Signatures in a Constrained Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Joye , Pascal Paillier , Serge Vaudenay Efficient Generation of Prime Numbers. [Citation Graph (0, 0)][DBLP ] Conf ] 