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Conferences in DBLP

Cryptographic Hardware and Embedded Systems (CHES) (ches)
2002 (conf/ches/2002)

  1. Jean-Jacques Quisquater
    CHES: Past, Present, and Future. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:1- [Conf]
  2. Sergei P. Skorobogatov, Ross J. Anderson
    Optical Fault Induction Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:2-12 [Conf]
  3. Suresh Chari, Josyula R. Rao, Pankaj Rohatgi
    Template Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:13-28 [Conf]
  4. Dakshi Agrawal, Bruce Archambeault, Josyula R. Rao, Pankaj Rohatgi
    The EM Side-Channel(s). [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:29-45 [Conf]
  5. Shay Gueron
    Enhanced Montgomery Multiplication. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:46-56 [Conf]
  6. Róbert Lórencz
    New Algorithm for Classical Modular Inverse. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:57-70 [Conf]
  7. Wieland Fischer, Jean-Pierre Seifert
    Increasing the Bitlength of a Crypto-Coprocessor. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:71-81 [Conf]
  8. Elisabeth Oswald
    Enhancing Simple Power-Analysis Attacks on Elliptic Curve Cryptosystems. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:82-97 [Conf]
  9. Elena Trichina, Antonio Bellezza
    Implementation of Elliptic Curve Cryptography with Built-In Counter Measures against Side Channel Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:98-113 [Conf]
  10. Catherine H. Gebotys, Robert J. Gebotys
    Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:114-128 [Conf]
  11. Kouichi Itoh, Tetsuya Izu, Masahiko Takenaka
    Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:129-143 [Conf]
  12. A. K. Lutz, J. Treichler, Frank K. Gürkaynak, Hubert Kaeslin, G. Basler, Antonia Erni, S. Reichmuth, P. Rommens, Stephan Oetiker, Wolfgang Fichtner
    2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:144-158 [Conf]
  13. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Stefano Marchesin
    Efficient Software Implementation of AES on 32-Bit Platforms. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:159-171 [Conf]
  14. Sumio Morioka, Akashi Satoh
    An Optimized S-Box Circuit Architecture for Low Power AES Design. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:172-186 [Conf]
  15. Elena Trichina, Domenico De Seta, Lucia Germani
    Simplified Adaptive Multiplicative Masking for AES. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:187-197 [Conf]
  16. Jovan Dj. Golic, Christophe Tymen
    Multiplicative Masking and Power Analysis of AES. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:198-212 [Conf]
  17. Andrew Huang
    Keeping Secrets in Hardware: The Microsoft Xbox™ Case Study. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:213-227 [Conf]
  18. Bert den Boer, Kerstin Lemke, Guntram Wicke
    A DPA Attack against the Modular Reduction within a CRT Implementation of RSA. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:228-243 [Conf]
  19. Vlastimil Klíma, Tomás Rosa
    Further Results and Considerations on Side Channel Attacks on RSA. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:244-259 [Conf]
  20. Christian Aumüller, Peter Bier, Wieland Fischer, Peter Hofreiter, Jean-Pierre Seifert
    Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:260-275 [Conf]
  21. Colin D. Walter
    Some Security Aspects of the M IST Randomized Exponentiation Algorithm. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:276-290 [Conf]
  22. Marc Joye, Sung-Ming Yen
    The Montgomery Powering Ladder. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:291-302 [Conf]
  23. Kouichi Itoh, Jun Yajima, Masahiko Takenaka, Naoya Torii
    DPA Countermeasures by Improving the Window Method. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:303-317 [Conf]
  24. Martijn Stam, Arjen K. Lenstra
    Efficient Subgroup Exponentiation in Quadratic and Sixth Degree Extensions. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:318-332 [Conf]
  25. Elisavet Konstantinou, Yannis C. Stamatiou, Christos D. Zaroliagis
    On the Efficient Generation of Elliptic Curves over Prime Fields. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:333-348 [Conf]
  26. Nils Gura, Sheueling Chang Shantz, Hans Eberle, Sumit Gupta, Vipul Gupta, Daniel Finchelstein, Edouard Goupy, Douglas Stebila
    An End-to-End Systems Approach to Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:349-365 [Conf]
  27. Richard Schroeppel, Cheryl L. Beaver, Rita Gonzales, Russell Miller, Timothy Draelos
    A Low-Power Design for an Elliptic Curve Digital Signature Chip. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:366-380 [Conf]
  28. M. Ernst, M. Jung, F. Madlener, S. Huss, Rainer Blümel
    A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n). [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:381-399 [Conf]
  29. N. Boston, T. Clancy, Y. Liow, J. Webster
    Genus Two Hyperelliptic Curve Coprocessor. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:400-414 [Conf]
  30. Viktor Fischer, Milos Drutarovský
    True Random Number Generator Embedded in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:415-430 [Conf]
  31. Werner Schindler, Wolfgang Killmann
    Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:431-449 [Conf]
  32. Thomas E. Tkacik
    A Hardware Random Number Generator. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:450-453 [Conf]
  33. Sanjay E. Sarma, Stephen A. Weis, Daniel W. Engels
    RFID Systems and Security and Privacy Implications. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:454-469 [Conf]
  34. Alexander Klimov, Adi Shamir
    A New Class of Invertible Mappings. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:470-483 [Conf]
  35. Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, Erkay Savas, Çetin Kaya Koç
    Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2). [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:484-499 [Conf]
  36. Johannes Wolkerstorfer
    Dual-Field Arithmetic Unit for GF(p) and GF(2m). [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:500-514 [Conf]
  37. Arash Reyhani-Masoleh, M. Anwarul Hasan
    Error Detection in Polynomial Basis Multipliers over Binary Extension Fields. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:515-528 [Conf]
  38. Dan Page, Nigel P. Smart
    Hardware Implementation of Finite Fields of Characteristic Three. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:529-539 [Conf]
  39. Mathieu Ciet, Jean-Jacques Quisquater, Francesco Sica
    Preventing Differential Analysis in GLV Elliptic Curve Scalar Multiplication. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:540-550 [Conf]
  40. JaeCheol Ha, Sang-Jae Moon
    Randomized Signed-Scalar Multiplication of ECC to Resist Power Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:551-563 [Conf]
  41. Katsuyuki Okeya, Kouichi Sakurai
    Fast Multi-scalar Multiplication Methods on Elliptic Curves with Precomputation Strategy Using Montgomery Trick. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:564-578 [Conf]
  42. Richard Clayton, Mike Bond
    Experience Using a Low-Cost FPGA Design to Crack DES Keys. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:579-592 [Conf]
  43. François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
    A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:593-609 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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