
Conferences in DBLP
 Cédric Archambeau, Eric Peeters, FrançoisXavier Standaert, JeanJacques Quisquater
Template Attacks in Principal Subspaces. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:114 [Conf]
 Benedikt Gierlichs, Kerstin LemkeRust, Christof Paar
Templates vs. Stochastic Methods. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:1529 [Conf]
 FrançoisXavier Standaert, Eric Peeters, Cédric Archambeau, JeanJacques Quisquater
Towards Security Limits in SideChannel Attacks. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:3045 [Conf]
 Deukjo Hong, Jaechul Sung, Seokhie Hong, Jongin Lim, Sangjin Lee, Bonseok Koo, Changhoon Lee, Donghoon Chang, Jesang Lee, Kitae Jeong, Hyun Kim, Jongsung Kim, Seongtaek Chee
HIGHT: A New Block Cipher Suitable for LowResource Device. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:4659 [Conf]
 Kazumaro Aoki
Integer Factoring Utilizing PC Cluster. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:60 [Conf]
 Sergei P. Skorobogatov
Optically Enhanced PositionLocked Power Analysis. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:6175 [Conf]
 Stefan Mangard, Kai Schramm
Pinpointing the SideChannel Leakage of Masked AES Hardware Implementations. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:7690 [Conf]
 Amir Moradi, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh
A Generalized Method of Differential Fault Attack Against AES Cryptosystem. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:91100 [Conf]
 Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
Breaking Ciphers with COPACOBANA  A CostOptimized Parallel Code Breaker. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:101118 [Conf]
 Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi
Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:119133 [Conf]
 Michael Scott, Neil Costigan, Wesam Abdulwahab
Implementing Cryptographic Pairings on Smartcards. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:134147 [Conf]
 Toru Akishita, Masanobu Katagi, Izuru Kitamura
SPAResistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:148159 [Conf]
 Marc Joye, Pascal Paillier
Fast Generation of Prime Numbers on Portable Devices: An Update. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:160173 [Conf]
 ThanhHa Le, Jessy Clédière, Cécile Canovas, Bruno Robisson, Christine Servière, JeanLouis Lacoume
A Proposition for Correlation Power Analysis Enhancement. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:174186 [Conf]
 Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
HighResolution SideChannel Attack Using PhaseBased Waveform Matching. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:187200 [Conf]
 Joseph Bonneau, Ilya Mironov
CacheCollision Timing Attacks Against AES. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:201215 [Conf]
 Emmanuel Prouff, Christophe Giraud, Sébastien Aumônier
Provably Secure SBox Implementation Based on Fourier Transform. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:216230 [Conf]
 Ari Juels
The Outer Limits of RFID Security. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:231 [Conf]
 Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
ThreePhase DualRail Precharge Logic. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:232241 [Conf]
 Zhimin Chen, Yujie Zhou
DualRail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:242254 [Conf]
 Daisuke Suzuki, Minoru Saeki
Security Evaluation of DPA Countermeasures Using DualRail Precharge Logic Style. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:255269 [Conf]
 Stefan Tillich, Johann Großschädl
Instruction Set Extensions for Efficient AES Implementation on 32bit Processors. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:270284 [Conf]
 Massoud Masoumi, Farshid Raissi, Mahmoud Ahmadian
NanoCMOSMolecular Realization of Rijndael. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:285297 [Conf]
 Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
Improving SHA2 Hardware Implementations. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:298310 [Conf]
 Eric Simpson, Patrick Schaumont
Offline Hardware/Software Authentication for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:311323 [Conf]
 Eric Brier, Benoît ChevallierMames, Mathieu Ciet, Christophe Clavier
Why One Should Also Secure RSA Public Key Elements. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:324338 [Conf]
 PierreAlain Fouque, Sébastien KunzJacques, Gwenaëlle Martinet, Frédéric Muller, Frédéric Valette
Power Attack on Small RSA Public Exponent. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:339353 [Conf]
 Douglas Stebila, Nicolas Thériault
Unified Point Addition Formulæ and SideChannel Attacks. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:354368 [Conf]
 Pim Tuyls, Geert Jan Schrijen, Boris Skoric, Jan van Geloven, Nynke Verhaegh, Rob Wolters
ReadProof Hardware from Protective Coatings. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:369383 [Conf]
 G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:384398 [Conf]
 Konrad J. Kulikowski, Alexander Smirnov, Alexander Taubin
Automated Design of Cryptographic Devices Resistant to Multiple SideChannel Attacks. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:399413 [Conf]
 AhmadReza Sadeghi
Challenges for Trusted Computing. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:414 [Conf]
 Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
Superscalar Coprocessor for HighSpeed CurveBased Cryptography. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:415429 [Conf]
 Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer
Hardware/Software Codesign of Elliptic Curve Cryptography on an 8051 Microcontroller. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:430444 [Conf]
 V. S. Dimitrov, Kimmo U. Järvinen, M. J. Jacobson, W. F. Chan, Z. Huang
FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers. [Citation Graph (0, 0)][DBLP] CHES, 2006, pp:445459 [Conf]
