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Conferences in DBLP

Cryptographic Hardware and Embedded Systems (CHES) (ches)
2006 (conf/ches/2006)

  1. Cédric Archambeau, Eric Peeters, François-Xavier Standaert, Jean-Jacques Quisquater
    Template Attacks in Principal Subspaces. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:1-14 [Conf]
  2. Benedikt Gierlichs, Kerstin Lemke-Rust, Christof Paar
    Templates vs. Stochastic Methods. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:15-29 [Conf]
  3. François-Xavier Standaert, Eric Peeters, Cédric Archambeau, Jean-Jacques Quisquater
    Towards Security Limits in Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:30-45 [Conf]
  4. Deukjo Hong, Jaechul Sung, Seokhie Hong, Jongin Lim, Sangjin Lee, Bonseok Koo, Changhoon Lee, Donghoon Chang, Jesang Lee, Kitae Jeong, Hyun Kim, Jongsung Kim, Seongtaek Chee
    HIGHT: A New Block Cipher Suitable for Low-Resource Device. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:46-59 [Conf]
  5. Kazumaro Aoki
    Integer Factoring Utilizing PC Cluster. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:60- [Conf]
  6. Sergei P. Skorobogatov
    Optically Enhanced Position-Locked Power Analysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:61-75 [Conf]
  7. Stefan Mangard, Kai Schramm
    Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:76-90 [Conf]
  8. Amir Moradi, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh
    A Generalized Method of Differential Fault Attack Against AES Cryptosystem. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:91-100 [Conf]
  9. Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
    Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:101-118 [Conf]
  10. Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi
    Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:119-133 [Conf]
  11. Michael Scott, Neil Costigan, Wesam Abdulwahab
    Implementing Cryptographic Pairings on Smartcards. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:134-147 [Conf]
  12. Toru Akishita, Masanobu Katagi, Izuru Kitamura
    SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:148-159 [Conf]
  13. Marc Joye, Pascal Paillier
    Fast Generation of Prime Numbers on Portable Devices: An Update. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:160-173 [Conf]
  14. Thanh-Ha Le, Jessy Clédière, Cécile Canovas, Bruno Robisson, Christine Servière, Jean-Louis Lacoume
    A Proposition for Correlation Power Analysis Enhancement. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:174-186 [Conf]
  15. Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:187-200 [Conf]
  16. Joseph Bonneau, Ilya Mironov
    Cache-Collision Timing Attacks Against AES. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:201-215 [Conf]
  17. Emmanuel Prouff, Christophe Giraud, Sébastien Aumônier
    Provably Secure S-Box Implementation Based on Fourier Transform. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:216-230 [Conf]
  18. Ari Juels
    The Outer Limits of RFID Security. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:231- [Conf]
  19. Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
    Three-Phase Dual-Rail Pre-charge Logic. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:232-241 [Conf]
  20. Zhimin Chen, Yujie Zhou
    Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:242-254 [Conf]
  21. Daisuke Suzuki, Minoru Saeki
    Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:255-269 [Conf]
  22. Stefan Tillich, Johann Großschädl
    Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:270-284 [Conf]
  23. Massoud Masoumi, Farshid Raissi, Mahmoud Ahmadian
    NanoCMOS-Molecular Realization of Rijndael. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:285-297 [Conf]
  24. Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
    Improving SHA-2 Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:298-310 [Conf]
  25. Eric Simpson, Patrick Schaumont
    Offline Hardware/Software Authentication for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:311-323 [Conf]
  26. Eric Brier, Benoît Chevallier-Mames, Mathieu Ciet, Christophe Clavier
    Why One Should Also Secure RSA Public Key Elements. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:324-338 [Conf]
  27. Pierre-Alain Fouque, Sébastien Kunz-Jacques, Gwenaëlle Martinet, Frédéric Muller, Frédéric Valette
    Power Attack on Small RSA Public Exponent. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:339-353 [Conf]
  28. Douglas Stebila, Nicolas Thériault
    Unified Point Addition Formulæ and Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:354-368 [Conf]
  29. Pim Tuyls, Geert Jan Schrijen, Boris Skoric, Jan van Geloven, Nynke Verhaegh, Rob Wolters
    Read-Proof Hardware from Protective Coatings. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:369-383 [Conf]
  30. G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
    Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:384-398 [Conf]
  31. Konrad J. Kulikowski, Alexander Smirnov, Alexander Taubin
    Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:399-413 [Conf]
  32. Ahmad-Reza Sadeghi
    Challenges for Trusted Computing. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:414- [Conf]
  33. Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Superscalar Coprocessor for High-Speed Curve-Based Cryptography. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:415-429 [Conf]
  34. Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer
    Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:430-444 [Conf]
  35. V. S. Dimitrov, Kimmo U. Järvinen, M. J. Jacobson, W. F. Chan, Z. Huang
    FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:445-459 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002