Conferences in DBLP

(fdl)
2008 (conf/fdl/2008)

1. 
   Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. [Citation Graph (, )][DBLP]
   
   
2. 
   Modelling Program-State Machines in SystemC. [Citation Graph (, )][DBLP]
   
   
3. 
   Extending SystemC Clocks to Model SoC. [Citation Graph (, )][DBLP]
   
   
4. 
   Efficient Modelling and Simulation of Embedded Software Multi-Tasking using SystemC and OSSS. [Citation Graph (, )][DBLP]
   
   
5. 
   Connecting SystemC-AMS Models with OSCI TLM 2.0 Models using Temporal Decoupling. [Citation Graph (, )][DBLP]
   
   
6. 
   Towards a Common HW/SW Interface-Centric and Component-Oriented Specification and Design Methodology. [Citation Graph (, )][DBLP]
   
   
7. 
   A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. [Citation Graph (, )][DBLP]
   
   
8. 
   Application - Platform Performance Modeling and Evaluation. [Citation Graph (, )][DBLP]
   
   
9. 
   A SystemC-based Framework for Modeling and Simulation of Networked Embedded Systems. [Citation Graph (, )][DBLP]
   
   
10. 
    A SystemC Language Extension for High-Level Reconfiguration Modelling. [Citation Graph (, )][DBLP]
    
    
11. 
    Specification of Adaptive HW/SW Systems in SystemC. [Citation Graph (, )][DBLP]
    
    
12. 
    Towards Compilation of Streaming Programs into FPGA Hardware. [Citation Graph (, )][DBLP]
    
    
13. 
    Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). [Citation Graph (, )][DBLP]
    
    
14. 
    Designing Highly Parameterized Hardware using xHdl. [Citation Graph (, )][DBLP]
    
    
15. 
    Formal Transformation of a KPN Specification to a GALS Implementation. [Citation Graph (, )][DBLP]
    
    
16. 
    A Sigma-delta Bandpass ADC Modelling in Superconducting RSFQ Technology with VHDL-AMS. [Citation Graph (, )][DBLP]
    
    
17. 
    VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation. [Citation Graph (, )][DBLP]
    
    
18. 
    SystemC-AMS Modeling of an Electromechanical Harvester of Vibration Energy. [Citation Graph (, )][DBLP]
    
    
19. 
    Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties. [Citation Graph (, )][DBLP]
    
    
20. 
    A Requirements-Driven Simulation Framework for Communication Infrastructures Design. [Citation Graph (, )][DBLP]
    
    
21. 
    VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. [Citation Graph (, )][DBLP]
    
    
22. 
    Modeling of Custom-Designed Arithmetic Components for ABL Normalization. [Citation Graph (, )][DBLP]
    
    
23. 
    Contradiction Analysis for Constraint-based Random Simulation. [Citation Graph (, )][DBLP]
    
    
24. 
    The Performance of Combining Multiway Decision Graphs and HOL Theorem Prover. [Citation Graph (, )][DBLP]
    
    
25. 
    A Contract-based Formalism for the Specification of Heterogeneous Systems (invited). [Citation Graph (, )][DBLP]
    
    
26. 
    Synthesizing Software Defined Radio Components from Rosetta (invited). [Citation Graph (, )][DBLP]
    
    
27. 
    Event-Triggered vs. Time-Triggered Communications with UML MARTE. [Citation Graph (, )][DBLP]
    
    
28. 
    MARTE-based Design of a Multimedia Application and Formal Analysis. [Citation Graph (, )][DBLP]
    
    
29. 
    UML 2.0 Interactions with OCL/RT Constraints. [Citation Graph (, )][DBLP]
    
    
30. 
    Refining Power Consumption Estimations in the Component-based AADL Design Flow. [Citation Graph (, )][DBLP]
    
    
31. 
    Model Driven Hardware Design: One Step Forward to Cope with the Aerospace Industry Needs. [Citation Graph (, )][DBLP]
    
    
32. 
    UML Profile for Modeling Product Observation. [Citation Graph (, )][DBLP]
    
    
33. 
    Scenario-based Validation of Embedded Systems. [Citation Graph (, )][DBLP]
    
    
34. 
    A Model Driven Development Approach for Implementing Reactive Systems in Hardware. [Citation Graph (, )][DBLP]
    
    
35. 
    Model-based Design Space Exploration for RTES with SysML and MARTE. [Citation Graph (, )][DBLP]
    
    
36. 
    Enabling Automated Code Transformation and Variable Tracing. [Citation Graph (, )][DBLP]
    
    
37. 
    Generating MARTE Allocation Models from Activity Threads. [Citation Graph (, )][DBLP]
    
    
38. 
    Using SystemC for an Extended MATLAB/Simulink Verification Flow. [Citation Graph (, )][DBLP]
    
    
39. 
    Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). [Citation Graph (, )][DBLP]
    
    
40. 
    Comparison of ASCET and UML - Preparations for an Abstract Software Architecture. [Citation Graph (, )][DBLP]
    
    
41. 
    System Behaviour Capture: from UML to SystemC. [Citation Graph (, )][DBLP]
    
    
42. 
    A Platform for Requirement Based Formal Specification. [Citation Graph (, )][DBLP]
    
    
43. 
    Using C# Attributes to Describe Hardware Artefacts within Kiwi. [Citation Graph (, )][DBLP]
    
    
44. 
    Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study. [Citation Graph (, )][DBLP]
    
    
45. 
    SpecScribe Analog - A Specification Tool Extension for Heterogeneous Systems. [Citation Graph (, )][DBLP]
    
    
46. 
    Automotive System Design with Specification and Verification of Uncertainties. [Citation Graph (, )][DBLP]
    
    
47. 
    Statistical Modeling with SystemC-AMS for Automotive Systems. [Citation Graph (, )][DBLP]
    
    
48. 
    The AutoSUN Verification Environment. [Citation Graph (, )][DBLP]
    
    
49. 
    RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. [Citation Graph (, )][DBLP]
    
    
50. 
    Formal Specification of Delta MINs for MPSOC in the ACL2 Logic. [Citation Graph (, )][DBLP]
    
    
51. 
    TLM-Based Verification of a Combined Switching Networks-on-Chip Router. [Citation Graph (, )][DBLP]