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Conferences in DBLP

(fdl)
2007 (conf/fdl/2007)


  1. Non-Linear Circuit Simulation using MATLAB. [Citation Graph (, )][DBLP]


  2. Mixed-Level Modeling Using Configurable MOS Transistor Models. [Citation Graph (, )][DBLP]


  3. An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations. [Citation Graph (, )][DBLP]


  4. SystemC-WMS modeling of control techniques for switching amplifiers targeting polar RF transmitters. [Citation Graph (, )][DBLP]


  5. Proposal for a Bond Graph Based Model of Computation in SystemC-AMS. [Citation Graph (, )][DBLP]


  6. A general approach to the interoperability of HetSC and SystemC-AMS. [Citation Graph (, )][DBLP]


  7. Range Arithmetics to Speed up Reachability Analysis of Analog Systems. [Citation Graph (, )][DBLP]


  8. Statistical Modeling with VHDL-AMS. [Citation Graph (, )][DBLP]


  9. APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. [Citation Graph (, )][DBLP]


  10. Modeling Field Bus Communications for Automotive Applications. [Citation Graph (, )][DBLP]


  11. Efficient Transient Simulation of Lossy Coupled Interconnects in Digital Communication Applications. [Citation Graph (, )][DBLP]


  12. Common HDL-Matlab Simulation Environment. [Citation Graph (, )][DBLP]


  13. Modelling Alternatives for Cycle Approximate Bus TLMs. [Citation Graph (, )][DBLP]


  14. Protocol Bus Modeling using inheritance with TLM2.0. [Citation Graph (, )][DBLP]


  15. Combinatorial Dependencies in Transaction Level Models. [Citation Graph (, )][DBLP]


  16. Transaction Level Modelling: A reflection on what TLM is and how TLMs may be classified. [Citation Graph (, )][DBLP]


  17. How Different are Esterel and SystemC?. [Citation Graph (, )][DBLP]


  18. Autometic Generation of SystemC Transactors from AsmL Specification. [Citation Graph (, )][DBLP]


  19. Timed Asynchronous Circuits Modeling using SystemC. [Citation Graph (, )][DBLP]


  20. CSP with Synthesisable SystemC(tm) and OSSS. [Citation Graph (, )][DBLP]


  21. SystemC-based Simulation of the MICAS Architecture. [Citation Graph (, )][DBLP]


  22. Mapping Actor-Oriented Models to TLM Architectures. [Citation Graph (, )][DBLP]


  23. C-based System Development of Asynchronous Distributed Systems. [Citation Graph (, )][DBLP]


  24. An Integrated SystemC Debugging Environment. [Citation Graph (, )][DBLP]


  25. Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. [Citation Graph (, )][DBLP]


  26. Algorithmic Test Generation - a New Approach to testbench Creation. [Citation Graph (, )][DBLP]


  27. A Domain Specific Language for Cryptography. [Citation Graph (, )][DBLP]


  28. The Unified Models Methodology: Applications to Inkjet Printing. [Citation Graph (, )][DBLP]


  29. A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. [Citation Graph (, )][DBLP]


  30. Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. [Citation Graph (, )][DBLP]


  31. UML and SystemC - Comparison and Mapping Rules for Automatic Code Generation. [Citation Graph (, )][DBLP]


  32. A complete SystemC UML profile with dynamic features for behavioral descriptions. [Citation Graph (, )][DBLP]


  33. SC2 StateCharts to SystemC: Automatic Executable Models Generation. [Citation Graph (, )][DBLP]


  34. SystemC workload model generation from UML for performance simulation. [Citation Graph (, )][DBLP]


  35. A Metamodeling based Framework for Architectural Modeling and Simulator Generation. [Citation Graph (, )][DBLP]


  36. Compiling UML State Diagrams into VHDL: An Experiment in Using Model Driven Development. [Citation Graph (, )][DBLP]


  37. Mapping SysML to SystemC. [Citation Graph (, )][DBLP]


  38. Software Real-time Resource Modeling. [Citation Graph (, )][DBLP]


  39. Modeling Embedded Software Platforms with a UML Profile. [Citation Graph (, )][DBLP]


  40. Model-driven development of embedded system on heterogeneous platforms. [Citation Graph (, )][DBLP]


  41. Modeling of immediate vs. delayed data communications: from AADL to UML Marte. [Citation Graph (, )][DBLP]


  42. Model Transformations from a Data Parallel Formalism towards Synchronous Languages. [Citation Graph (, )][DBLP]


  43. Automatic High Level Assertion Generation and Synthesis for Embedded System Design. [Citation Graph (, )][DBLP]


  44. Time Modeling in MARTE. [Citation Graph (, )][DBLP]


  45. MARTE: UML-based Hardware Design from Modelling to Simulation. [Citation Graph (, )][DBLP]


  46. Repetitive Allocation Modelling with MARTE. [Citation Graph (, )][DBLP]


  47. Asynchronous online-monitoring of logical and temporal assertions. [Citation Graph (, )][DBLP]


  48. A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set. [Citation Graph (, )][DBLP]


  49. Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL. [Citation Graph (, )][DBLP]


  50. Grid Based Fast Falsification For Bounded Property Checking. [Citation Graph (, )][DBLP]


  51. Transactor-based Formal Verification of Real-time Embedded Systems. [Citation Graph (, )][DBLP]


  52. Verification of the Properties of Asynchronous Real-Time Distributed Systems using the B-Formalism. [Citation Graph (, )][DBLP]

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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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