Conferences in DBLP
(fdl) 2005 (conf/fdl/2005)
ENIAC & ARTEMIS Technology Platforms. [Citation Graph (, )][DBLP ] Trends and Challenges in Avionics Electronics. [Citation Graph (, )][DBLP ] Analitic Performance Analysis of Distributed Embedded Systems. [Citation Graph (, )][DBLP ] SystemC-Based Communication and Performance Analysis. [Citation Graph (, )][DBLP ] Application of SystemC/SystemC-AMS for the Specification of Complex Wired Telecomunication Systems. [Citation Graph (, )][DBLP ] SystemC-WMS: A Wave Mixed Signal Simulator. [Citation Graph (, )][DBLP ] System model of an inertial navigation system using SystemC-AMS. [Citation Graph (, )][DBLP ] AMS Extensions for Timed/Untimed System-Level Design Language. [Citation Graph (, )][DBLP ] Modelling Technologies for Disruptive Communication System Design. [Citation Graph (, )][DBLP ] UML/XML based approach to hierarchical AMS Synthesis. [Citation Graph (, )][DBLP ] Development of VHDL-AMS Libraries for Automative Applications. [Citation Graph (, )][DBLP ] Top-down hierarchical design flow application. [Citation Graph (, )][DBLP ] Semi-Symbollic Simulation of Nonlinear Systems. [Citation Graph (, )][DBLP ] Tolerance Models in Hardware Description Languages. [Citation Graph (, )][DBLP ] Jitter Tolerance Analysis of Clock and Data Recovery Circuits. [Citation Graph (, )][DBLP ] Linearly graded behavioural analogue performance models. [Citation Graph (, )][DBLP ] Automatic Generation of a Verification Platform. [Citation Graph (, )][DBLP ] Toward seamless top-down of A/MS systems. [Citation Graph (, )][DBLP ] Incorporating SystemC in Analog/Mixed-Signal Design Flow. [Citation Graph (, )][DBLP ] VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP. [Citation Graph (, )][DBLP ] VHDL-AMS virtual prototyping in power electronics. [Citation Graph (, )][DBLP ] VHDL-AMS Modelling and System Verification Flow. [Citation Graph (, )][DBLP ] A VHDL-AMS based Time-Domain Skin Depth Model. [Citation Graph (, )][DBLP ] Creating Virtual Prototypes of Complex Micro-Electro-Mechanical Transducers using Reduced-Order Modelling Methods and VHDL-AMS. [Citation Graph (, )][DBLP ] Overcoming issues to reach full adoption and benefit of C/C++based system design methodologies in real System-on-Chip projects. [Citation Graph (, )][DBLP ] OCP TLM for Architectural Modelling. [Citation Graph (, )][DBLP ] Devices modelling in SystemC based on behaviour separation. [Citation Graph (, )][DBLP ] Building heterogeneous plaftorm simulators in C++. [Citation Graph (, )][DBLP ] Implementation of a SystemC based Environment. [Citation Graph (, )][DBLP ] Executable Specification of Novel Display Controllers. [Citation Graph (, )][DBLP ] Mapping Interface Method Calls over OCP Buses. [Citation Graph (, )][DBLP ] SOAP Based Distributed Simulation Environment for SoC Design. [Citation Graph (, )][DBLP ] Modelling Environment for Heterogeneous Systems based on MoCs. [Citation Graph (, )][DBLP ] Processor Centric Specification and Modelling of MPSoCs. [Citation Graph (, )][DBLP ] Mixing Synchronous Reactive and Untimed Models of Computation. [Citation Graph (, )][DBLP ] Interface-Centric Abstraction Level for Rapid HW/SW Integration. [Citation Graph (, )][DBLP ] SystemCmantic: A high level Modelling and Co-Design Framework. [Citation Graph (, )][DBLP ] Hardware Synthesis of Parallel Machines from SystemC. [Citation Graph (, )][DBLP ] Towards Behavioural Hierarchy Extensions for SystemC. [Citation Graph (, )][DBLP ] Embed Scripting inside SystemC. [Citation Graph (, )][DBLP ] Efficient and Customizable Integration of Temporal Properties. [Citation Graph (, )][DBLP ] Aspect Orientation in System Level Design. [Citation Graph (, )][DBLP ] Automatic synthesis of the Hardware/Software Interface. [Citation Graph (, )][DBLP ] SystemCXML: An Exstensible SystemC Front end Using XML. [Citation Graph (, )][DBLP ] C-Based Hardware Design for Wireless Applications . [Citation Graph (, )][DBLP ] Leveraging the efficiency of C-Based Design with Catapult-C . [Citation Graph (, )][DBLP ] An Application of Generalized Supervisor Synthesis to the Control of a Call Center. [Citation Graph (, )][DBLP ] Modelling Heterogeneous Embedded Systems in DFCarts. [Citation Graph (, )][DBLP ] Refinement of Perfectly Synchronous Communication Model. [Citation Graph (, )][DBLP ] PSL-based online monitoring of digital systems. [Citation Graph (, )][DBLP ] Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. [Citation Graph (, )][DBLP ] IpPROCESS: a Development Process for Soft IP-Cord. [Citation Graph (, )][DBLP ] Meta Modelling of Embedded Systems using Active Databases. [Citation Graph (, )][DBLP ] Using feature models to automate model transformations. [Citation Graph (, )][DBLP ] An HW/SW Co-design Environment based on UML and SystemC. [Citation Graph (, )][DBLP ] Compiled and Synthesized UML, a practical Approach for Codesign. [Citation Graph (, )][DBLP ] Synthesis for Unified Control- and Data-Oriented Models. [Citation Graph (, )][DBLP ] Traceability and Interoperability in Models Transformations. [Citation Graph (, )][DBLP ] Power Modelling and Simulation Flow for Communication Protocols. [Citation Graph (, )][DBLP ] Integrating Model-Checking with UML-based SoC Development. [Citation Graph (, )][DBLP ] Formal Evaluation of Quality of Service for Data Acquisition. [Citation Graph (, )][DBLP ] The SysML profile for embedded system modelling. [Citation Graph (, )][DBLP ] Architecture description in related standards. [Citation Graph (, )][DBLP ]