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Conferences in DBLP

(fdl)
2005 (conf/fdl/2005)


  1. ENIAC & ARTEMIS Technology Platforms. [Citation Graph (, )][DBLP]


  2. Trends and Challenges in Avionics Electronics. [Citation Graph (, )][DBLP]


  3. Analitic Performance Analysis of Distributed Embedded Systems. [Citation Graph (, )][DBLP]


  4. SystemC-Based Communication and Performance Analysis. [Citation Graph (, )][DBLP]


  5. Application of SystemC/SystemC-AMS for the Specification of Complex Wired Telecomunication Systems. [Citation Graph (, )][DBLP]


  6. SystemC-WMS: A Wave Mixed Signal Simulator. [Citation Graph (, )][DBLP]


  7. System model of an inertial navigation system using SystemC-AMS. [Citation Graph (, )][DBLP]


  8. AMS Extensions for Timed/Untimed System-Level Design Language. [Citation Graph (, )][DBLP]


  9. Modelling Technologies for Disruptive Communication System Design. [Citation Graph (, )][DBLP]


  10. UML/XML based approach to hierarchical AMS Synthesis. [Citation Graph (, )][DBLP]


  11. Development of VHDL-AMS Libraries for Automative Applications. [Citation Graph (, )][DBLP]


  12. Top-down hierarchical design flow application. [Citation Graph (, )][DBLP]


  13. Semi-Symbollic Simulation of Nonlinear Systems. [Citation Graph (, )][DBLP]


  14. Tolerance Models in Hardware Description Languages. [Citation Graph (, )][DBLP]


  15. Jitter Tolerance Analysis of Clock and Data Recovery Circuits. [Citation Graph (, )][DBLP]


  16. Linearly graded behavioural analogue performance models. [Citation Graph (, )][DBLP]


  17. Automatic Generation of a Verification Platform. [Citation Graph (, )][DBLP]


  18. Toward seamless top-down of A/MS systems. [Citation Graph (, )][DBLP]


  19. Incorporating SystemC in Analog/Mixed-Signal Design Flow. [Citation Graph (, )][DBLP]


  20. VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP. [Citation Graph (, )][DBLP]


  21. VHDL-AMS virtual prototyping in power electronics. [Citation Graph (, )][DBLP]


  22. VHDL-AMS Modelling and System Verification Flow. [Citation Graph (, )][DBLP]


  23. A VHDL-AMS based Time-Domain Skin Depth Model. [Citation Graph (, )][DBLP]


  24. Creating Virtual Prototypes of Complex Micro-Electro-Mechanical Transducers using Reduced-Order Modelling Methods and VHDL-AMS. [Citation Graph (, )][DBLP]


  25. Overcoming issues to reach full adoption and benefit of C/C++based system design methodologies in real System-on-Chip projects. [Citation Graph (, )][DBLP]


  26. OCP TLM for Architectural Modelling. [Citation Graph (, )][DBLP]


  27. Devices modelling in SystemC based on behaviour separation. [Citation Graph (, )][DBLP]


  28. Building heterogeneous plaftorm simulators in C++. [Citation Graph (, )][DBLP]


  29. Implementation of a SystemC based Environment. [Citation Graph (, )][DBLP]


  30. Executable Specification of Novel Display Controllers. [Citation Graph (, )][DBLP]


  31. Mapping Interface Method Calls over OCP Buses. [Citation Graph (, )][DBLP]


  32. SOAP Based Distributed Simulation Environment for SoC Design. [Citation Graph (, )][DBLP]


  33. Modelling Environment for Heterogeneous Systems based on MoCs. [Citation Graph (, )][DBLP]


  34. Processor Centric Specification and Modelling of MPSoCs. [Citation Graph (, )][DBLP]


  35. Mixing Synchronous Reactive and Untimed Models of Computation. [Citation Graph (, )][DBLP]


  36. Interface-Centric Abstraction Level for Rapid HW/SW Integration. [Citation Graph (, )][DBLP]


  37. SystemCmantic: A high level Modelling and Co-Design Framework. [Citation Graph (, )][DBLP]


  38. Hardware Synthesis of Parallel Machines from SystemC. [Citation Graph (, )][DBLP]


  39. Towards Behavioural Hierarchy Extensions for SystemC. [Citation Graph (, )][DBLP]


  40. Embed Scripting inside SystemC. [Citation Graph (, )][DBLP]


  41. Efficient and Customizable Integration of Temporal Properties. [Citation Graph (, )][DBLP]


  42. Aspect Orientation in System Level Design. [Citation Graph (, )][DBLP]


  43. Automatic synthesis of the Hardware/Software Interface. [Citation Graph (, )][DBLP]


  44. SystemCXML: An Exstensible SystemC Front end Using XML. [Citation Graph (, )][DBLP]


  45. C-Based Hardware Design for Wireless Applications . [Citation Graph (, )][DBLP]


  46. Leveraging the efficiency of C-Based Design with Catapult-C . [Citation Graph (, )][DBLP]


  47. An Application of Generalized Supervisor Synthesis to the Control of a Call Center. [Citation Graph (, )][DBLP]


  48. Modelling Heterogeneous Embedded Systems in DFCarts. [Citation Graph (, )][DBLP]


  49. Refinement of Perfectly Synchronous Communication Model. [Citation Graph (, )][DBLP]


  50. PSL-based online monitoring of digital systems. [Citation Graph (, )][DBLP]


  51. Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. [Citation Graph (, )][DBLP]


  52. IpPROCESS: a Development Process for Soft IP-Cord. [Citation Graph (, )][DBLP]


  53. Meta Modelling of Embedded Systems using Active Databases. [Citation Graph (, )][DBLP]


  54. Using feature models to automate model transformations. [Citation Graph (, )][DBLP]


  55. An HW/SW Co-design Environment based on UML and SystemC. [Citation Graph (, )][DBLP]


  56. Compiled and Synthesized UML, a practical Approach for Codesign. [Citation Graph (, )][DBLP]


  57. Synthesis for Unified Control- and Data-Oriented Models. [Citation Graph (, )][DBLP]


  58. Traceability and Interoperability in Models Transformations. [Citation Graph (, )][DBLP]


  59. Power Modelling and Simulation Flow for Communication Protocols. [Citation Graph (, )][DBLP]


  60. Integrating Model-Checking with UML-based SoC Development. [Citation Graph (, )][DBLP]


  61. Formal Evaluation of Quality of Service for Data Acquisition. [Citation Graph (, )][DBLP]


  62. The SysML profile for embedded system modelling. [Citation Graph (, )][DBLP]


  63. Architecture description in related standards. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002