Conferences in DBLP

(sasp)
2008 (conf/sasp/2008)

1. 
   Custom Processor Core Construction from C Code. [Citation Graph (, )][DBLP]
   
   
2. 
   Resource Sharing in Custom Instruction Set Extensions. [Citation Graph (, )][DBLP]
   
   
3. 
   Custom Instruction Generation with High-Level Synthesis. [Citation Graph (, )][DBLP]
   
   
4. 
   Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. [Citation Graph (, )][DBLP]
   
   
5. 
   Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP]
   
   
6. 
   Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. [Citation Graph (, )][DBLP]
   
   
7. 
   An FPGA Design Space Exploration Tool for Matrix Inversion Architectures. [Citation Graph (, )][DBLP]
   
   
8. 
   Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. [Citation Graph (, )][DBLP]
   
   
9. 
   Extensible On-Chip Peripherals. [Citation Graph (, )][DBLP]
   
   
10. 
    Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. [Citation Graph (, )][DBLP]
    
    
11. 
    Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems. [Citation Graph (, )][DBLP]
    
    
12. 
    An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints. [Citation Graph (, )][DBLP]
    
    
13. 
    AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. [Citation Graph (, )][DBLP]
    
    
14. 
    Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating. [Citation Graph (, )][DBLP]
    
    
15. 
    System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis. [Citation Graph (, )][DBLP]
    
    
16. 
    Accelerating Compute-Intensive Applications with GPUs and FPGAs. [Citation Graph (, )][DBLP]
    
    
17. 
    TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing. [Citation Graph (, )][DBLP]
    
    
18. 
    Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer. [Citation Graph (, )][DBLP]
    
    
19. 
    An MDCT Hardware Accelerator for MP3 Audio. [Citation Graph (, )][DBLP]