Conferences in DBLP

(sasp)
2009 (conf/sasp/2009)

1. 
   Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication. [Citation Graph (, )][DBLP]
   
   
2. 
   Workload adaptive shared memory multicore processors with reconfigurable interconnects. [Citation Graph (, )][DBLP]
   
   
3. 
   A dataflow-centric approach to design low power control paths in CGRAs. [Citation Graph (, )][DBLP]
   
   
4. 
   A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip. [Citation Graph (, )][DBLP]
   
   
5. 
   Power-efficient medical image processing using PUMA. [Citation Graph (, )][DBLP]
   
   
6. 
   FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. [Citation Graph (, )][DBLP]
   
   
7. 
   A memory optimization technique for software-managed scratchpad memory in GPUs. [Citation Graph (, )][DBLP]
   
   
8. 
   Register Multimapping: A technique for reducing register bank conflicts in processors with large register files. [Citation Graph (, )][DBLP]
   
   
9. 
   Arithmetic optimization for custom instruction set synthesis. [Citation Graph (, )][DBLP]
   
   
10. 
    A new addressing mode for the encoding space problem on embedded processors. [Citation Graph (, )][DBLP]
    
    
11. 
    Driver assistance system design and its optimization for FPGA based MPSoC. [Citation Graph (, )][DBLP]
    
    
12. 
    Hardware acceleration of multi-view face detection. [Citation Graph (, )][DBLP]
    
    
13. 
    A multi-FPGA accelerator for radiation dose calculation in cancer treatment. [Citation Graph (, )][DBLP]
    
    
14. 
    A reconfigurable beamformer for audio applications. [Citation Graph (, )][DBLP]
    
    
15. 
    Parade: A versatile parallel architecture for accelerating pulse train clustering. [Citation Graph (, )][DBLP]
    
    
16. 
    A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs. [Citation Graph (, )][DBLP]
    
    
17. 
    Dynamic and application-driven I-cache partitioning for low-power embedded multitasking. [Citation Graph (, )][DBLP]
    
    
18. 
    A hardware-software codesign strategy for Loop intensive applications. [Citation Graph (, )][DBLP]
    
    
19. 
    Introducing control-flow inclusion to support pipelining in custom instruction set extensions. [Citation Graph (, )][DBLP]