Conferences in DBLP
(sips) A highly parallel Turbo Product Code decoder without interleaving resource. [Citation Graph (, )][DBLP ] A digit-serial architecture for inversion and multiplication in GF(2M ). [Citation Graph (, )][DBLP ] Unified decoder architecture for LDPC/turbo codes. [Citation Graph (, )][DBLP ] Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down. [Citation Graph (, )][DBLP ] A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. [Citation Graph (, )][DBLP ] A unified instruction set programmable architecture for multi-standard advanced forward error correction. [Citation Graph (, )][DBLP ] A method for improving the efficiency of a two-level memory hierarchy. [Citation Graph (, )][DBLP ] Hardware acceleration for tracking by computing low-order geometric moments. [Citation Graph (, )][DBLP ] Efficient image reconstruction using partial 2D Fourier transform. [Citation Graph (, )][DBLP ] Parallel channel interleavers for 3GPP2/UMB. [Citation Graph (, )][DBLP ] New simplified sum-product algorithm for low complexity LDPC decoding. [Citation Graph (, )][DBLP ] A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels. [Citation Graph (, )][DBLP ] Location-Constrained Particle Filter human positioning and tracking system. [Citation Graph (, )][DBLP ] Cooperative OFDM for energy-efficient wireless sensor networks. [Citation Graph (, )][DBLP ] High-throughput dual-mode single/double binary map processor design for wireless wan. [Citation Graph (, )][DBLP ] Trade-off analysis of decoding algorithms and architectures for multi-standard LDPC decoder. [Citation Graph (, )][DBLP ] Error correction for multi-level NAND flash memory using Reed-Solomon codes. [Citation Graph (, )][DBLP ] Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding. [Citation Graph (, )][DBLP ] Two-dimensional crosstalk avoidance codes. [Citation Graph (, )][DBLP ] Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis. [Citation Graph (, )][DBLP ] An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders. [Citation Graph (, )][DBLP ] Reduced-complexity MSGR-based matrix inversion. [Citation Graph (, )][DBLP ] Kalman filtering based motion estimation for video coding with adaptive block partitioning. [Citation Graph (, )][DBLP ] Fast multiple reference frame selection methods for H.264/AVC. [Citation Graph (, )][DBLP ] Minimal complexity low-latency architectures for Viterbi decoders. [Citation Graph (, )][DBLP ] Efficient ordering schemes for sphere decoder. [Citation Graph (, )][DBLP ] Analysis of belief propagation for hardware realization. [Citation Graph (, )][DBLP ] Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition. [Citation Graph (, )][DBLP ] Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding framework. [Citation Graph (, )][DBLP ] On the verification of multi-standard SoC'S for reconfigurable video coding based on algorithm/architecture co-exploration. [Citation Graph (, )][DBLP ] Efficient realization of a cal video decoder on a mobile terminal (position paper). [Citation Graph (, )][DBLP ] Scheduling of dataflow models within the Reconfigurable Video Coding framework. [Citation Graph (, )][DBLP ] Efficient data flow variable length decoding implementation for the MPEG reconfigurable video coding framework. [Citation Graph (, )][DBLP ] Defect-tolerant digital filtering with unreliable molecular electronics. [Citation Graph (, )][DBLP ] Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks. [Citation Graph (, )][DBLP ] DSP implementation of probabilistic sound source localization. [Citation Graph (, )][DBLP ] Soft decoder architecture of LT codes. [Citation Graph (, )][DBLP ] Low-complexity high-speed 4-D TCM decoder. [Citation Graph (, )][DBLP ] Error-resilient low-power Viterbi decoders via state clustering. [Citation Graph (, )][DBLP ] Further cost reduction of adaptive echo and next cancellers for high-speed Ethernet transceivers. [Citation Graph (, )][DBLP ] Power efficient dynamic-range utilisation for DSP on FPGA. [Citation Graph (, )][DBLP ] Hierarchical run time deadlock detection in process networks. [Citation Graph (, )][DBLP ] Application-driven adaptive fixed-point refinement for SDRs. [Citation Graph (, )][DBLP ] Low-complexity polynomials modulo integer with linearly incremented variable. [Citation Graph (, )][DBLP ] SmartCell: A power-efficient reconfigurable architecture for data streaming applications. [Citation Graph (, )][DBLP ] The support of software design patterns for streaming RPC on embedded multicore processors. [Citation Graph (, )][DBLP ] Efficient mapping of advanced signal processing algorithms on multi-processor architectures. [Citation Graph (, )][DBLP ] Parallelization of AdaBoost algorithm on multi-core processors. [Citation Graph (, )][DBLP ] Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study. [Citation Graph (, )][DBLP ] Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study. [Citation Graph (, )][DBLP ] Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding framework. [Citation Graph (, )][DBLP ] 