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Conferences in DBLP

International Conference on Hardware Software Codesign (codes)
1998 (conf/codes/1998)

  1. Pai H. Chou, Gaetano Borriello
    An analysis-based approach to composition of distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:3-7 [Conf]
  2. Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele
    Combining multiple models of computation for scheduling and allocation. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:9-13 [Conf]
  3. Claudio Passerone, Roberto Passerone, Claudio Sansoè, Jonathan Martin, Alberto L. Sangiovanni-Vincentelli, Rick McGeer
    Modeling reactive systems in Java. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:15-19 [Conf]
  4. Jörg Henkel, Yanbing Li
    Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:23-27 [Conf]
  5. Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
    HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:29-33 [Conf]
  6. Franz Fischer, Annette Muth, Georg Färber
    Towards interprocess communication and interface synthesis for a heterogeneous real-time rapid prototyping environment. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:35-39 [Conf]
  7. Michael Eisenring, Jürgen Teich
    Domain-specific interface generation from dataflow specifications. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:43-47 [Conf]
  8. Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet
    Communication synthesis and HW/SW integration for embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:49-53 [Conf]
  9. Peter Voigt Knudsen, Jan Madsen
    Communication estimation for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:55-59 [Conf]
  10. Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli
    Software timing analysis using HW/SW cosimulation and instruction set simulator. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:65-69 [Conf]
  11. Sungjoo Yoo, Kiyoung Choi
    Optimistic distributed timed cosimulation based on thread simulation model. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:71-75 [Conf]
  12. Giuseppe Del Castillo, Wolfram Hardt
    Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:77-81 [Conf]
  13. Luc Bianco, Michel Auguin, Guy Gogniat, Alain Pegatoquet
    A path analysis based partitioning for time constrained embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:85-89 [Conf]
  14. Frank Slomka, Jürgen Zant, Lennard Lambert
    Schedulability analysis of heterogeneous systems for performance message sequence chart. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:91-95 [Conf]
  15. Robert P. Dick, David L. Rhodes, Wayne Wolf
    TGFF: task graphs for free. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:97-101 [Conf]
  16. Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
    A hardware/software prototyping environment for dynamically reconfigurable embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:105-109 [Conf]
  17. Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ahmed Amine Jerraya
    Hardware/software co-design of an ATM network interface card: a case study. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:111-115 [Conf]
  18. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    A case study on modeling shared memory access effects during performance analysis of HW/SW systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:117-121 [Conf]
  19. Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
    The construction of a retargetable simulator for an architecture template. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:125-129 [Conf]
  20. Jian Li, Rajesh K. Gupta
    HDL code restructuring using timed decision tables. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:131-135 [Conf]
  21. Karam S. Chatha, Ranga Vemuri
    RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:139-143 [Conf]
  22. Peter Grun, Florin Balasa, Nikil D. Dutt
    Memory size estimation for multimedia applications. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:145-149 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002