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Conferences in DBLP

International Conference on Hardware Software Codesign (codes)
2002 (conf/codes/2002)

  1. Brian Grattan, Greg Stitt, Frank Vahid
    Codesign-extended applications. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:1-6 [Conf]
  2. Todor Stefanov, Bart Kienhuis, Ed F. Deprettere
    Algorithmic transformation techniques for efficient exploration of alternative application instances. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:7-12 [Conf]
  3. Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang
    Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:13-18 [Conf]
  4. JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas
    The design context of concurrent computation systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:19-24 [Conf]
  5. Dag Björklund, Johan Lilius
    A language for multiple models of computation. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:25-30 [Conf]
  6. Per Bjuréus, Mikael Millberg, Axel Jantsch
    FPGA resource and timing estimation from Matlab execution traces. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:31-36 [Conf]
  7. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Worst-case performance analysis of parallel, communicating software processes. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:37-42 [Conf]
  8. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Symbolic model checking of Dual Transition Petri Nets. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:43-48 [Conf]
  9. G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy
    Simulation bridge: a framework for multi-processor simulation. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:49-54 [Conf]
  10. Donatella Sciuto, Fabio Salice, Luigi Pomante, William Fornaciari
    Metrics for design space exploration of heterogeneous multiprocessor embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:55-60 [Conf]
  11. Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell
    Fast processor core selection for WLAN modem using mappability estimation. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:61-66 [Conf]
  12. Maurizio Palesi, Tony Givargis
    Multi-objective design space exploration using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:67-72 [Conf]
  13. Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel
    Scratchpad memory: design alternative for cache on-chip memory in embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:73-78 [Conf]
  14. Mohamed Shalan, Vincent John Mooney III
    Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:79-84 [Conf]
  15. Abdenour Azzedine, Jean-Philippe Diguet, Jean-Luc Pillippe
    Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:85-90 [Conf]
  16. Jeffry T. Russell
    Program slicing for codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:91-96 [Conf]
  17. T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua
    Compiler-directed customization of ASIP cores. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:97-102 [Conf]
  18. Avishay Orpaz, Shlomo Weiss
    A study of CodePack: optimizing embedded code space. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:103-108 [Conf]
  19. Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss
    A novel codesign approach based on distributed virtual machines. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:109-114 [Conf]
  20. Massimiliano Chiodo
    Optimization and synthesis for complex reactive embedded systems by incremental collapsing. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:115-120 [Conf]
  21. Marek Jersak, Kai Richter, Rafik Henia, Rolf Ernst, Frank Slomka
    Transformation of SDL specifications for system-level timing analysis. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:121-126 [Conf]
  22. Ali Dasdan
    A strongly polynomial-time algorithm for over-constraint resolution: efficient debugging of timing constraint violations. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:127-132 [Conf]
  23. Hyunok Oh, Soonhoi Ha
    Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:133-138 [Conf]
  24. Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol
    Design of multi-tasking coprocessor control for Eclipse. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:139-144 [Conf]
  25. Daler N. Rakhmatov, Sarma B. K. Vrudhula
    Hardware-software bipartitioning for dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:145-150 [Conf]
  26. Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:151-156 [Conf]
  27. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast system-level power profiling for battery-efficient system design. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:157-162 [Conf]
  28. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    Energy savings through compression in embedded Java environments. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:163-168 [Conf]
  29. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
    Communication speed selection for embedded systems with networked voltage-scalable processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:169-174 [Conf]
  30. Vishnu Swaminathan, Krishnendu Chakrabarty
    Pruning-based energy-optimal device scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:175-180 [Conf]
  31. Peter Petrov, Alex Orailoglu
    Energy frugal tags in reprogrammable I-caches for application-specific embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:181-186 [Conf]
  32. Traian Pop, Petru Eles, Zebo Peng
    Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:187-192 [Conf]
  33. Ismail Kadayif, Mahmut T. Kandemir, Ibrahim Kolcu, Guangyu Chen
    Locality-conscious process scheduling in embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:193-198 [Conf]
  34. Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi
    Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:199-204 [Conf]
  35. Juanjo Noguera, Rosa M. Badia
    Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:205-210 [Conf]
  36. Feng-Shi Su, Pao-Ann Hsiung
    Extended quasi-static scheduling for formal synthesis and code generation of embedded software. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:211-216 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002