Conferences in DBLP
Youngmin Yi , Dohyung Kim , Soonhoi Ha Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Kogel , Malte Doerper , Andreas Wieferink , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Serge Goossens A modular simulation framework for architectural exploration of on-chip interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Reshadi , Nikhil Bansal , Prabhat Mishra , Nikil D. Dutt An efficient retargetable framework for instruction-set simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Lukai Cai , Daniel Gajski Transaction level modeling: an overview. [Citation Graph (0, 0)][DBLP ] Conf ] Eike Grimpe , Frank Oppenheimer Extending the SystemC synthesis subset by object-oriented features. [Citation Graph (0, 0)][DBLP ] Conf ] Haobo Yu , Andreas Gerstlauer , Daniel Gajski RTOS scheduling in transaction level models. [Citation Graph (0, 0)][DBLP ] Conf ] Shaojie Wang , Sharad Malik Synthesizing operating system based device drivers in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Kohout , Brinda Ganesh , Bruce L. Jacob Hardware support for real-time operating systems. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Zhao , Jie Liu , Jim Reich , Maurice Chu , Juan Liu Programming embedded networked sensor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Ming Lim , M. Benaissa Design space exploration of a hardware-software co-designed GF(2m ) galois field processor for forward error correction and cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Arezou Koohi , Nader Bagherzadeh , Chengzi Pan A fast parallel reed-solomon decoder on a reconfigurable architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Hagen , Daniel A. Connors , Bryan L. Pellom The analysis and design of architecture systems for speech recognition on modern handheld-computing devices. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano , Mark Underseth , Faraydon Karim Industry best practices in embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Doug Burger Architectural versus physical solutions for on-chip communication challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli On-chip communication design: roadblocks and avenues. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yiping Fan , Guoling Han , Xun Yang , Zhiru Zhang Architecture and synthesis for multi-cycle on-chip communication. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , Grant Martin System-level design tools: who needs them, who has them, and how much should they cost? [Citation Graph (0, 0)][DBLP ] Conf ] Mojy C. Chian Driving forces behind SOC development. [Citation Graph (0, 0)][DBLP ] Conf ] Nik Dutt , Janos Sztipanovits , Masaki Hirata Driving agenda for systems research. [Citation Graph (0, 0)][DBLP ] Conf ] Traian Pop , Petru Eles , Zebo Peng Design optimization of mixed time/event-triggered distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Todor Stefanov , Ed F. Deprettere Deriving process networks from weakly dynamic applications in system-level design. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Peset Llopis , Ramanathan Sethuraman , Carlos A. Alba Pinto , Harm Peters , Steffen Maul , Marcel Oosterhuis A low-cost and low-power multi-standard video encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Behzad Mohebbi , Eliseu Chavez Filho , Rafael Maestre , Mark Davies , Fadi J. Kurdahi A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. [Citation Graph (0, 0)][DBLP ] Conf ] Roman L. Lysecky , Frank Vahid A codesigned on-chip logic minimizer. [Citation Graph (0, 0)][DBLP ] Conf ] Pao-Ann Hsiung , Cheng-Yi Lin Synthesis of real-time embedded software with local and global deadlines. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Yang , Francky Catthoor Pareto-optimization-based run-time task scheduling for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] N. Ranganathan , Ashok K. Murugavel A low power scheduler using game theory. [Citation Graph (0, 0)][DBLP ] Conf ] Ananth Hegde , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin VL-CDRAM: variable line sized cached DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Chanik Park , Jaeyu Seo , Sunghwan Bae , Hyojun Kim , Shinhan Kim , Bumsoo Kim A low-cost memory architecture with NAND XIP for mobile embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Qingfeng Zhuge , Zili Shao , Bin Xiao , Edwin Hsing-Mean Sha Design space minimization with timing and code size optimization for embedded DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , Youngsoo Shin , Nagu R. Dhanwada , Subhrajit Bhattacharya , William E. Dougherty , Indira Nair , John A. Darringer , Sarala Paliwal SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] JoAnn M. Paul Programmers' views of SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys , Y. Zhang Security wrappers and power analysis for SoC technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Susan Cotterell , Frank Vahid , Walid A. Najjar , Harry Hsieh First results with eBlocks: embedded systems building blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Tarvo Raudvere , Ingo Sander , Ashish Kumar Singh , Axel Jantsch Verification of design decisions in ForSyDe. [Citation Graph (0, 0)][DBLP ] Conf ] Cagkan Erbas , Selin C. Erbas , Andy D. Pimentel A multiobjective optimization model for exploring multiprocessor mappings of process networks. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Zimmer , Axel Jantsch A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] James Lin Design technology challenges for system and chip level designs in very deep submicron technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Sungchan Kim , Chaeseok Im , Soonhoi Ha Schedule-aware performance estimation of communication architecture for efficient design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Hemendra Singh Negi , Tulika Mitra , Abhik Roychoudhury Accurate estimation of cache-related preemption delay. [Citation Graph (0, 0)][DBLP ] Conf ] William Fornaciari , Fabio Salice , Daniele Paolo Scarpazza Early estimation of the size of VHDL projects. [Citation Graph (0, 0)][DBLP ] Conf ] Guangyu Chen , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin , Mario Wolczko Tracking object life cycle for leakage energy optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Björn Franke , Michael F. P. O'Boyle Compiler parallelization of C programs for multi-core DSPs with multiple address spaces. [Citation Graph (0, 0)][DBLP ] Conf ] Haiyong Xie , Li Zhao , Laxmi N. Bhuyan Architectural analysis and instruction-set optimization for design of network protocol processors. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , Grant Martin , Wayne Wolf , Rolf Ernst , Kees A. Vissers , Jack Kouloheris The future of system-level design: can we find the right solutions to the right problems at the right time? [Citation Graph (0, 0)][DBLP ] Conf ] 