|
|
Conferences in DBLP
- Stan Y. Liao
Towards a new standard for system-level design. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:2-6 [Conf]
- Axel Jantsch, Ingo Sander
On the roles of functions and objects in system specification. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:8-12 [Conf]
- Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
Compaan: deriving process networks from Matlab for embedded signal processing architectures. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:13-17 [Conf]
- João M. Fernandes, Ricardo Jorge Machado, Henrique D. Santos
Modeling industrial embedded systems with UML. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:18-22 [Conf]
- Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
Energy estimation for 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:24-28 [Conf]
- William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano
Power optimization of system-level address buses based on software profiling. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:29-33 [Conf]
- Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
Instruction-level power estimation for embedded VLIW cores. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:34-38 [Conf]
- Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
Low-power task scheduling for multiple devices. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:39-43 [Conf]
- Hua Lin, Wayne Wolf
Co-design of interleaved memory systems. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:46-50 [Conf]
- Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Steen Pedersen
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:51-55 [Conf]
- Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Storage requirement estimation for data intensive applications with partially fixed execution ordering. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:56-60 [Conf]
- Paul Pop, Petru Eles, Zebo Peng
Performance estimation for embedded systems with data and control dependencies. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:62-66 [Conf]
- Hiroyuki Tomiyama, Nikil D. Dutt
Program path analysis to bound cache-related preemption delay in preemptive real-time systems. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:67-71 [Conf]
- Xiaobo Sharon Hu, Gang Quan
Fast performance prediction for periodic task systems. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:72-76 [Conf]
- Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:77-81 [Conf]
- Jwahar R. Bammi, Wido Kruijtzer, Luciano Lavagno, Edwin A. Harcourt, Mihai T. Lazarescu
Software performance estimation strategies in a system-level design tool. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:82-86 [Conf]
- Olivier Hébert, Ivan C. Kraljic, Yvon Savaria
A method to derive application-specific embedded processing cores. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:88-92 [Conf]
- Matthias Meerwein, C. Baumgartner, W. Glauert
Linking codesign and reuse in embedded systems design. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:93-97 [Conf]
- Tony Givargis, Frank Vahid
Parameterized system design. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:98-102 [Conf]
- Frederik Vermeulen, Francky Catthoor, Diederik Verkest, Hugo De Man
Extended design reuse trade-offs in hardware-software architecture mapping. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:103-107 [Conf]
- Bassam Tabbara, Abdallah Tabbara, Alberto L. Sangiovanni-Vincentelli
Task response time optimization using cost-based operation motion. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:110-114 [Conf]
- R. Anand, Margarida F. Jacome, Gustavo de Veciana
Heuristic tradeoffs between latency and energy consumption in register assignment. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:115-119 [Conf]
- Haris Lekatsas, Jörg Henkel, Wayne Wolf
Code compression as a variable in hardware/software co-design. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:120-124 [Conf]
- Frank A. Engel, Johannes Nührenberg, Gerhard Fettweis
A generic tool set for application specific processor architectures. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:126-130 [Conf]
- JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
Frequency interleaving as a codesign scheduling paradigm. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:131-135 [Conf]
- Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Automatic test bench generation for simulation-based validation. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:136-140 [Conf]
- Joseph Buck, Radha Vaidyanathan
Heterogeneous modeling and simulation of embedded systems in El Greco. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:142-146 [Conf]
- Julio Leao da Silva Jr., Marco Sgroi, Fernando De Bernardinis, Suet-Fei Li, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey
Wireless protocols design: challenges and opportunities. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:147-151 [Conf]
- Deborah Wilson, Daniel Dayton, R. Todd Hansell
ASDEN: a comprehensive design framework vision for automotive electronic control systems. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:152-156 [Conf]
- Randall S. Janka, Linda M. Wills
A novel codesign methodology for real-time embedded COTS multiprocessor-based signal processing systems. [Citation Graph (0, 0)][DBLP]
CODES, 2000, pp:157-161 [Conf]
|
