Conferences in DBLP
Wayne Wolf CODES and co-design: a look back and a look forward. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Jantsch , Ingo Sander , Wenbiao Wu The usage of stochastic processes in embedded system specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Neal K. Tibrewala , JoAnn M. Paul , Donald E. Thomas Modeling and evaluation of hardware/software designs. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Fin , Franco Fummi , Maurizio Martignano , Mirko Signoretto SystemC: a homogenous environment to test embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Martin , Luciano Lavagno , Jean Louis-Guerin Embedded UML: a merger of real-time UML and co-design. [Citation Graph (0, 0)][DBLP ] Conf ] Geert Vanmeerbeeck , Patrick Schaumont , Serge Vernalde , Marc Engels , Ivo Bolsens Hardware/software partitioning of embedded system in OCAPI-xl. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss , Shay Beren HW/SW partitioning of an embedded instruction memory decompressor. [Citation Graph (0, 0)][DBLP ] Conf ] Karam S. Chatha , Ranga Vemuri MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Denis Hommais , Frédéric Pétrot , Ivan Augé A practical tool box for system level communication synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen K. Murthy , Etan G. Cohen , Steve Rowland System canvas: a new design environment for embedded DSP and telecommunication systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marnix Arnold , Henk Corporaal Designing domain-specific processors. [Citation Graph (0, 0)][DBLP ] Conf ] Cagdas Akturan , Margarida F. Jacome RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Pun H. Shiu , Yudong Tan , Vincent John Mooney III A novel parallel deadlock detection algorithm and architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Towards effective embedded processors in codesigns: customizable partitioned caches. [Citation Graph (0, 0)][DBLP ] Conf ] William Fornaciari , Fabio Salice , Umberto Bondi , Edi Magini Development cost and size estimation starting from high-level specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Basant Kumar Dwivedi , Jan Hoogerbrugge , Paul Stravers , M. Balakrishnan Exploring design space of parallel realizations: MPEG-2 decoder case study. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Brandolese , William Fornaciari , Fabio Salice , Donatella Sciuto Source-level execution time estimation of C programs. [Citation Graph (0, 0)][DBLP ] Conf ] Felice Balarin STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar Jain , Lars Wehmeyer , Stefan Steinke , Peter Marwedel , M. Balakrishnan Evaluating register file size in ASIP design. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Slomka , Matthias Dörfel , Ralf Münzenberger Generating mixing hardware/software systems from SDL specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Kyoungseok Rha , Kiyoung Choi Area-efficient buffer binding based on a novel two-port FIFO structure. [Citation Graph (0, 0)][DBLP ] Conf ] José M. Álvarez , Manuel Díaz , Luis Llopis , Ernesto Pimentel , José M. Troya Deriving hard real-time embedded systems implementations directly from SDL specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Lieverse , Pieter van der Wolf , Ed F. Deprettere A trace transformation technique for communication refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Lioupis , Apostolos Papagiannis , Dionysia Psihogiou A systematic approach to software peripherals for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski A constructive algorithm for memory-aware task assignment and scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Jinfeng Liu , Pai H. Chou , Nader Bagherzadeh , Fadi J. Kurdahi A constraint-based application model and scheduling techniques for power-aware systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sid Ahmed Ali Touati Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sungtaek Lim , Jihong Kim , Kiyoung Choi Scheduling-based code size reduction in processors with indirect addressing mode. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Wong , Paul Marchal , Peng Yang Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi Parameterised system design based on genetic algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Pop , Petru Eles , Traian Pop , Zebo Peng Minimizing system modification in an incremental design approach. [Citation Graph (0, 0)][DBLP ] Conf ] André Chátelain , Yves Mathys , Giovanni Placido , Alberto La Rosa , Luciano Lavagno High-level architectural co-simulation using Esterel and C. [Citation Graph (0, 0)][DBLP ] Conf ] Sungjoo Yoo , Gabriela Nicolescu , Damien Lyonnard , Amer Baghdadi , Ahmed Amine Jerraya A generic wrapper architecture for multi-processor SoC cosimulation and design. [Citation Graph (0, 0)][DBLP ] Conf ] Seppo Virtanen , Johan Lilius The TACO protocol processor simulation environment. [Citation Graph (0, 0)][DBLP ] Conf ] Pao-Ann Hsiung Formal synthesis and code generation of embedded real-time software. [Citation Graph (0, 0)][DBLP ] Conf ] Johan Cockx Whole program compilation for embedded software: the ADSL experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Ismail Kadayif Compiler-directed selection of dynamic memory layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Yunjian Jiang , Robert K. Brayton Logic optimization and code generation for embedded control applications. [Citation Graph (0, 0)][DBLP ] Conf ] Royan H. L. Ong , Michael J. Pont Empirical comparison of software-based error detection and correction techniques for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu Swaminathan , Krishnendu Chakrabarty , S. Sitharama Iyengar Dynamic I/O power management for hard real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Neal K. Bambha , Shuvra S. Bhattacharyya , Jürgen Teich , Eckart Zitzler Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Acquaviva , Luca Benini , Bruno Riccò Processor frequency setting for energy minimization of streaming multimedia application. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Tsong Shiue Retargetable compilation for low power. [Citation Graph (0, 0)][DBLP ] Conf ] William Fornaciari , Donatella Sciuto , Cristina Silvano , Vittorio Zaccaria A design framework to efficiently explore energy-delay tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] 