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Conferences in DBLP

International Conference on Hardware Software Codesign (codes)
2004 (conf/codes/2004)

  1. Andrea Cuomo
    Future challenges in embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:1- [Conf]
  2. Christian Müller-Schloer
    Organic computing: on the feasibility of controlled emergence. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:2-5 [Conf]
  3. Binu K. Mathew, Al Davis
    A loop accelerator for low power embedded VLIW processors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:6-11 [Conf]
  4. Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
    Dual-pipeline heterogeneous ASIP design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:12-17 [Conf]
  5. Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer
    Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:18-23 [Conf]
  6. Hyunuk Jung, Soonhoi Ha
    Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:24-29 [Conf]
  7. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:30-35 [Conf]
  8. Vladimir Kotlyar, Mayan Moudgill
    Detecting overflow detection. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:36-41 [Conf]
  9. Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
    Memory accesses management during high level synthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:42-47 [Conf]
  10. Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu
    Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:48-53 [Conf]
  11. JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
    Benchmark-based design strategies for single chip heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:54-59 [Conf]
  12. Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
    Automatic synthesis of system on chip multiprocessor architectures for process networks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:60-65 [Conf]
  13. Xinping Zhu, Wei Qin, Sharad Malik
    Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:66-71 [Conf]
  14. Peter Marwedel, Catherine H. Gebotys
    Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:72- [Conf]
  15. Sven Mattisson
    Keynote: cellular handset technology system requirements and integration trends. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:74- [Conf]
  16. Adam Donlin
    Transaction level modeling: flows and use models. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:75-80 [Conf]
  17. Luigi Pomante
    Exploiting polymorphism in HW design: a case study in the ATM domain. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:81-85 [Conf]
  18. Manish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August
    Facilitating reuse in hardware models with enhanced type inference. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:86-91 [Conf]
  19. Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata
    System-on-chip validation using UML and CWL. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:92-97 [Conf]
  20. Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen
    Compiler-directed code restructuring for reducing data TLB energy. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:98-103 [Conf]
  21. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Dynamic overlay of scratchpad memory for energy minimization. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:104-109 [Conf]
  22. Haisang Wu, Binoy Ravindran, E. Douglas Jensen, Peng Li
    CPU scheduling for statistically-assured real-time performance and improved energy efficiency. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:110-115 [Conf]
  23. Juanjo Noguera, Rosa M. Badia
    Power-performance trade-offs for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:116-121 [Conf]
  24. Sudarshan Banerjee, Nikil D. Dutt
    Efficient search space exploration for HW-SW partitioning. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:122-127 [Conf]
  25. Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong
    Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:128-133 [Conf]
  26. Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang
    Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:134-139 [Conf]
  27. Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
    Memory system design space exploration for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:140-145 [Conf]
  28. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    Analytical models for leakage power estimation of memory array structures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:146-151 [Conf]
  29. Luca Formaggio, Franco Fummi, Graziano Pravadelli
    A timing-accurate HW/SW co-simulation of an ISS with SystemC. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:152-157 [Conf]
  30. Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada
    RTOS-centric hardware/software cosimulator for embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:158-163 [Conf]
  31. Zhengting He, Aloysius K. Mok
    Fast co-simulation of transformative systems with OS support on SMP computer. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:164-169 [Conf]
  32. Dongkun Shin, Jihong Kim
    Power-aware communication optimization for networks-on-chips with voltage scalable links. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:170-175 [Conf]
  33. Erland Nilsson, Johnny Öberg
    Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:176-181 [Conf]
  34. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Multi-objective mapping for mesh-based NoC architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:182-187 [Conf]
  35. Paul Marchal, José Ignacio Gómez, Francky Catthoor
    Optimizing the memory bandwidth with loop fusion. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:188-193 [Conf]
  36. Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau
    Operation tables for scheduling in the presence of incomplete bypassing. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:194-199 [Conf]
  37. Jaehwan Lee, Vincent John Mooney III
    A novel deadlock avoidance algorithm and its hardware implementation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:200-205 [Conf]
  38. Pieter van der Wolf, Erwin A. de Kock, Tomas Henriksson, Wido Kruijtzer, Gerben Essink
    Design and programming of embedded multiprocessors: an interface-centric approach. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:206-217 [Conf]
  39. Radu Muresan, Catherine H. Gebotys
    Current flattening in software and hardware for security applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:218-223 [Conf]
  40. Catherine H. Gebotys
    Low energy security optimization in embedded cryptographic systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:224-229 [Conf]
  41. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    Analyzing heap error behavior in embedded JVM environments. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:230-235 [Conf]
  42. Kanishka Lahiri, Anand Raghunathan
    Power analysis of system-level on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:236-241 [Conf]
  43. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Fast exploration of bus-based on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:242-247 [Conf]
  44. Sungchan Kim, Chaeseok Im, Soonhoi Ha
    Efficient exploration of on-chip bus architectures and memory allocation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:248-253 [Conf]
  45. Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist
    Embedded systems education: how to teach the required skills? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:254-255 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002