Conferences in DBLP
H. Peter Hofstee , Michael N. Day Hardware and software architectures for the CELL processor. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor N. Mudge Performance and power analysis of computer systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Muller The challenges of embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] Charlie Johnson , Jeff Welser Future processors: flexible and modular. [Citation Graph (0, 0)][DBLP ] Conf ] C. John Glossner , Mayan Moudgill , Daniel Iancu , Gary Nacer , Sanjay Jinturkar , Stuart Stanley , Michael Samori , Tanuj Raja , Michael J. Schulte , Stamatis Vassiliadis Future wireless convergence platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Wilmot A core flight software system. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Axel Siebenborn Conflict analysis in multiprocess synthesis for optimized system integration. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Reshadi , Daniel Gajski A cycle-accurate compilation algorithm for custom pipelined datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Vinu Vijay Kumar , John Lach Highly flexible multi-mode system synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Xiangrong Zhou , Peter Petrov Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Morgan , Richard Taylor , Japheth Hossell , George Bruce , Barry O'Rourke Automated data cache placement for embedded VLIW ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] Chuanjun Zhang An efficient direct mapped instruction cache for application-specific embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunok Oh , Nikil D. Dutt , Soonhoi Ha Shift buffering technique for automatic code synthesis from synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Henriksson , Jeffrey Kang , Pieter van der Wolf Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Scott J. Weber , Kurt Keutzer Using minimal minterms to represent programmability. [Citation Graph (0, 0)][DBLP ] Conf ] Ümit Y. Ogras , Jingcao Hu , Radu Marculescu Key research problems in NoC design: a holistic perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Hansson , Kees Goossens , Andrei Radulescu A unified approach to constrained mapping and routing on network-on-chip architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony Leroy , Paul Marchal , Adelina Shickova , Francky Catthoor , Frédéric Robert , Diederik Verkest Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir , Mary Jane Irwin Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Yang , Robert P. Dick , Haris Lekatsas , Srimat T. Chakradhar CRAMES: compressed RAM for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Costa , Erven Rohou Comparing the size of .NET applications with native code. [Citation Graph (0, 0)][DBLP ] Conf ] Fen Xie , Margaret Martonosi , Sharad Malik Efficient behavior-driven runtime dynamic voltage scaling policies. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Maxiaguine , Samarjit Chakraborty , Lothar Thiele DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] Antonis Papanikolaou , F. Lobmaier , Hua Wang , Miguel Miranda , Francky Catthoor A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Martin , Daniel Gajski , David Goodwin , Patrick Lysaght , Peter Marwedel , Mike Muller , Jeff Welser What will system level design be when it grows up? [Citation Graph (0, 0)][DBLP ] Conf ] Wido Kruijtzer , Winfried Gehrke , Víctor Reyes , Ghiath Alkadi , Thomas Hinz , Jorn Jöchalsky , Bruno Steux The design of a smart imaging core for automotive and consumer applications: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Shenglin Yang , Patrick Schaumont , Ingrid Verbauwhede Microcoded coprocessor for embedded secure biometric authentication systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vida Kianzad , Sankalita Saha , Jason Schlessman , Gaurav Aggarwal , Shuvra S. Bhattacharyya , Wayne Wolf , Rama Chellappa An architectural level design methodology for embedded face detection. [Citation Graph (0, 0)][DBLP ] Conf ] Nagu R. Dhanwada , Ing-Chao Lin , Vijay Narayanan A power estimation methodology for systemC transaction level models. [Citation Graph (0, 0)][DBLP ] Conf ] Sankalp Kallakuri , Alex Doboli Energy conscious online architecture adaptation for varying latency constraints in sensor network applications. [Citation Graph (0, 0)][DBLP ] Conf ] Aviral Shrivastava , Eugene Earlie , Nikil D. Dutt , Alexandru Nicolau Aggregating processor free time for energy reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Youfeng Wu , Mauricio Breternitz Jr. , Herbert H. J. Hum , Ramesh V. Peri , Jay Pickett Enhanced code density of embedded CISC processors with echo technology. [Citation Graph (0, 0)][DBLP ] Conf ] Pan Yu , Tulika Mitra Satisfying real-time constraints with custom instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Kubilay Atasu , Günhan Dündar , Can C. Özturan An integer linear programming approach for identifying instruction-set extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Inoue , Akihisa Ikeno , Masaki Kondo , Junji Sakai , Masato Edahiro FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Muresan , Haleh Vahedi , Y. Zhanrong , Stefano Gregori Power-smart system-on-chip architecture for embedded cryptosystems. [Citation Graph (0, 0)][DBLP ] Conf ] Divya Arora , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha Enhancing security through hardware-assisted run-time validation of program data properties. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob White Developing design tools for biological and biomedical applications of micro- and nano-technology. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty , Fei Su System-level design automation tools for digital microfluidic biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Robert S. Germain , Blake G. Fitch , Aleksandr Rayshubskiy , Maria Eleftheriou , Michael Pitman , Frank Suits , Mark Giampapa , T. J. Christopher Ward Blue matter on blue gene/L: massively parallel computation for biomolecular simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Quan , James P. Davis , Siddhaveerasharan Devarkal , Duncan A. Buell High-level synthesis for large bit-width multipliers on FPGAs: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Yang , Ramesh Karri Power optimization for universal hash function data path using divide-and-concatenate technique. [Citation Graph (0, 0)][DBLP ] Conf ] Peggy B. McGee , Steven M. Nowick , Edward G. Coffman Jr. Efficient performance analysis of asynchronous systems based on periodicity. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Venkataramani , Tiberiu Chelcea , Seth Copen Goldstein , Tobias Bjerregaard SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Reshadi , Prabhat Mishra Memory access optimizations in instruction-set simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Miljan Vuletic , Christophe Dubach , Laura Pozzi , Paolo Ienne Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Wieferink , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Tom Michiels , Achim Nohl , Tim Kogel Retargetable generation of TLM bus interfaces for MP-SoC platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwan Shin , Andreas Gerstlauer , Rainer Dömer , Daniel D. Gajski Automatic network generation for system-on-chip communication design. [Citation Graph (0, 0)][DBLP ] Conf ] Adriano Sarmento , Lobna Kriaa , Arnaud Grasset , Mohamed-Wassim Youssef , Aimen Bouchhima , Frédéric Rousseau , Wander O. Cesário , Ahmed Amine Jerraya Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Víctor Reyes , Tomás Bautista , Gustavo Marrero , Antonio Núñez , Wido Kruijtzer A multicast inter-task communication protocol for embedded multiprocessor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yujia Jin , Nadathur Satish , Kaushik Ravindran , Kurt Keutzer An automated exploration framework for FPGA-based soft multiprocessor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Ohlendorf , Andreas Herkersdorf , Thomas Wild FlexPath NP: a network processor concept with application-driven flexible processing paths. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Frank Vahid , Gordon McGregor , Brian Einloth Hardware/software partitioning of software binaries: a case study of H.264 decode. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Kim , Suleyman Sair Designing real-time H.264 decoders with dataflow architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Seng Lin Shee , Sri Parameswaran , Newton Cheung Novel architecture for loop acceleration: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Tenllado , Luis Piñuel , Manuel Prieto , Francisco Tirado , Francky Catthoor Improving superword level parallelism support in modern compilers. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Xue , Zili Shao , Meilin Liu , Edwin Hsing-Mean Sha Iterational retiming: maximize iteration-level parallelism for nested loops. [Citation Graph (0, 0)][DBLP ] Conf ] Jiwon Hahn , Qiang Xie , Pai H. Chou Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiano Pereira , Jeremy Lau , Brad Calder , Rajesh K. Gupta Dynamic phase analysis for cycle-close trace generation. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar L. Romero , Marius Strum , Wang Jiang Chau Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. [Citation Graph (0, 0)][DBLP ] Conf ] Janos Sztipanovits , C. John Glossner , Trevor N. Mudge , Chris Rowen , Alberto L. Sangiovanni-Vincentelli , Wayne Wolf , Feng Zhao Grand challenges in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] 