Conferences in DBLP
Wolfgang Mueller , Yves Vanderperren UML and model-driven development for SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshimi Furukawa , Seiji Kawamura Automotive electronics system, software, and local area network. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo Promises and challenges of mobile embedded system: : an industry perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Balaji Raman , Samarjit Chakraborty Application-specific workload shaping in multimedia-enabled personal mobile devices. [Citation Graph (0, 0)][DBLP ] Conf ] Maarten Wiggers , Marco Bekooij , Pierre Jansen , Gerard J. M. Smit Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure. [Citation Graph (0, 0)][DBLP ] Conf ] Minyoung Kim , Sudarshan Banerjee , Nikil Dutt , Nalini Venkatasubramanian Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Lipskoch , Karsten Albers , Frank Slomka Battery discharge aware energy feasibility analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Selim Gurun , Chandra Krintz A run-time, feedback-based energy estimation model For embedded devices. [Citation Graph (0, 0)][DBLP ] Conf ] Puru Choudhary , Diana Marculescu Hardware based frequency/voltage control of voltage frequency island systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arne Hamann , Razvan Racu , Rolf Ernst A formal approach to robustness maximization of complex heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ai-Hsin Liu , Robert P. Dick Automatic run-time extraction of communication graphs from multithreaded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Ik Ko , Shuvra S. Bhattacharyya The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Bombieri , Franco Fummi , Davide Quaglia TLM/network design space exploration for networked embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwan Shin , Andreas Gerstlauer , Junyu Peng , Rainer Dömer , Daniel D. Gajski Automatic generation of transaction level models for rapid design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Gunar Schirner , Rainer Dömer Accurate yet fast modeling of real-time communication. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Abdullah Al Faruque , Gereon Weiss , Jörg Henkel Bounded arbitration algorithm for QoS-supported on-chip communication. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Eun Lee , Nader Bagherzadeh Increasing the throughput of an adaptive router in network-on-chip (NoC). [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Scherrer , Antoine Fraboulet , Tanguy Risset Automatic phase detection for stochastic on-chip traffic generation. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys , B. A. White Methodology for attack on a Java-based PDA. [Citation Graph (0, 0)][DBLP ] Conf ] Roshan G. Ragel , Sri Parameswaran Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Divya Arora , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha Architectural support for safe software execution on embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Xu , Krishnendu Chakrabarty Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Gupta , Nikil D. Dutt , Fadi J. Kurdahi , Kamal S. Khouri , Magdy S. Abadir Floorplan driven leakage power aware IP-based SoC design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Pilok Lim , Taewhan Kim Thermal-aware high-level synthesis based on network flow method. [Citation Graph (0, 0)][DBLP ] Conf ] Martijn Coenen , Srinivasan Murali , Andrei Radulescu , Kees Goossens , Giovanni De Micheli A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Karam S. Chatha Layout aware design of mesh based NoC architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Palesi , Rickard Holsmark , Shashi Kumar , Vincenzo Catania A methodology for design of application specific deadlock-free routing algorithms for NoC systems. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Hohenauer , Christoph Schumacher , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Hans van Someren Retargetable code optimization with SIMD instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Tanaka , Yoshinori Takeuchi , Keishi Sakanushi , Masaharu Imai , Yutaka Ota , Nobu Matsumoto , Masaki Nakagawa Pack instruction generation for media pUsing multi-valued decision diagram. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Galuzzi , Elena Moscu Panainte , Yana Yankova , Koen Bertels , Stamatis Vassiliadis Automatic selection of application-specific instruction-set extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Teich Are current ESL tools meeting the requirements of advanced embedded systems? [Citation Graph (0, 0)][DBLP ] Conf ] Pier Stanislao Paolucci , Ahmed Amine Jerraya , Rainer Leupers , Lothar Thiele , Piero Vicini SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau , Milind Girkarmark , Xinmin Tian , Hideki Saito Challenges in exploitation of loop parallelism in embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher D. Gill Resource virtualization in real-time CORBA middleware. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Namkung , Dohyung Kim , Rajesh K. Gupta , Igor Kozintsev , Jean-Yves Bouget , Carole Dulong Phase guided sampling for efficient parallel application simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Qin , Joseph D'Errico , Xinping Zhu A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Wonbok Lee , Kimish Patel , Massoud Pedram B2 Sim: : a fast micro-architecture simulator based on basic block characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Beltrame , Dario Bruschi , Donatella Sciuto , Cristina Silvano Decision-theoretic exploration of multiProcessor platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Hristo Nikolov , Todor Stefanov , Ed F. Deprettere Multi-processor system design with ESPAM. [Citation Graph (0, 0)][DBLP ] Conf ] Seng Lin Shee , Andrea Erdos , Sri Parameswaran Heterogeneous multiprocessor implementations for JPEG: : a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro G. Di Nuovo , Maurizio Palesi , Davide Patti , Giuseppe Ascia , Vincenzo Catania Fuzzy decision making in embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] Yongsoo Joo , Yongseok Choi , Chanik Park , Sung Woo Chung , EuiYoung Chung , Naehyuck Chang Demand paging for OneNANDTM Flash eXecute-in-place. [Citation Graph (0, 0)][DBLP ] Conf ] Sungpack Hong , Sungjoo Yoo , Sheayun Lee , Sangwoo Lee , Hye Jeong Nam , Bum-Seok Yoo , Jaehyung Hwang , Donghyun Song , Janghwan Kim , Jeongeun Kim , HoonSang Jin , Kyu-Myung Choi , Jeong-Taek Kong , Soo-Kwan Eo Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. [Citation Graph (0, 0)][DBLP ] Conf ] Swarnalatha Radhakrishnan , Hui Guo , Sri Parameswaran , Aleksandar Ignjatovic Application specific forwarding network and instruction encoding for multi-pipe ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Wen Hsieh , Po-Yuan Chen , TingTing Hwang A bus architecture for crosstalk elimination in high performance processor design. [Citation Graph (0, 0)][DBLP ] Conf ] Antonis Papanikolaou , T. Grabner , Miguel Miranda , P. Roussel , Francky Catthoor Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations. [Citation Graph (0, 0)][DBLP ] Conf ] Hayden Kwok-Hay So , Artem Tkachenko , Robert W. Brodersen A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. [Citation Graph (0, 0)][DBLP ] Conf ] Krisztián Flautner Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kyung-Ho Kim Key technologies for the next generation wireless communications. [Citation Graph (0, 0)][DBLP ] Conf ] Manjunath Kudlur , Kevin Fan , Scott A. Mahlke Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Fan , Manjunath Kudlur , Hyunchul Park , Scott A. Mahlke Increasing hardware efficiency with multifunction loop accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Bita Gorjiara , Mehrdad Reshadi , Pramod Chandraiah , Daniel Gajski Generic netlist representation for system and PE level design exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Simon Schliecker , Matthias Ivers , Rolf Ernst Integrated analysis of communicating tasks in MPSoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Issenin , Nikil Dutt Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Young-Hwan Park , Fadi J. Kurdahi , Nikil D. Dutt System-level power-performance trade-offs in bus matrix communication architecture synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] 