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Conferences in DBLP

Embedded Systems and Applications (csreaESA)
2004 (conf/csreaESA/2004)

  1. Venkiteswaran Anantharam, Maojiao He, Krishna Natarajan, Huikai Xie, Michael P. Frank
    Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:5-11 [Conf]
  2. Ahmed Elkammar, Srinivasa Vemuru, Norman Scheinberg
    A Bus Encoding Scheme to Reduce Power Consuming Signal Transitions. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:12-17 [Conf]
  3. S. Castillo, Naveen K. Samala, K. Manwaring, Baback A. Izadi, Damu Radhakrishnan
    Experimental Analysis of Batteries Under Continuous and Intermittent Operations. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:18-24 [Conf]
  4. Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
    A Low Energy Deep Sub-Micron Bus Coding Technique. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:25-30 [Conf]
  5. Fun Ye, Jen-Shiun Chiang, Chun-Cheng Wu
    Low Power Sigma-Delta Modulator with Dynamic Biasing for Speech CODECs. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:31-35 [Conf]
  6. Cheng-Chih Chien, Jen-Shiun Chiang, Ming-Hung Tu, Yu-Cheng Sung, Yi-Tsung Lee
    Low-Power Switched-Capacitor Filters for Telecommunication Applications. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:36-39 [Conf]
  7. Yong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkumar, Damu Radhakrishnan
    A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:40-46 [Conf]
  8. R. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
    Switching Activity Minimization in Combinational Logic Design. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:47-53 [Conf]
  9. Jayapreetha Natesan, Damu Radhakrishnan
    A Novel Bus Encoding Technique for Low Power VLSI. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:54-62 [Conf]
  10. Keith S. Vallerio, Niraj K. Jha
    Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:63-69 [Conf]
  11. Matias Madou, Bjorn De Sutter, Bruno De Bus, Ludo Van Put, Koen De Bosschere
    Link-Time Compaction of MIPS Programs. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:70-75 [Conf]
  12. Darrin M. Hanna, Richard E. Haskell
    Implementing Software Programs in FPGAs Using Flowpaths. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:76-82 [Conf]
  13. Andrzej Bednarski, Christoph W. Keßler
    Exploiting Symmetries for Optimal Integrated Code Generation. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:83-92 [Conf]
  14. Niranjan Regatte, Carl Larsen, S. Jagannathan
    A New Fair Scheduling MAC Protocol for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:93-98 [Conf]
  15. T. L. Bharatheesh, S. Sitharama Iyengar
    Predictive Data Mining for Delinquency Modeling. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:99-105 [Conf]
  16. Sheikh Iqbal Ahamed, Avinash Vyas
    Challenges in Monitoring Sensor Networks and a Solution Framework. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:106-112 [Conf]
  17. Nader F. Mir
    A Self-Organizing Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:113-122 [Conf]
  18. David Zier, Jumnit Hong, Savithri Venkatachalapathy, Jarrod Nelson, John Mark Matson, Ben Lee, YoungHwan Bae, HanJin Cho
    X32V: A Design of Configurable Processor Core for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:123-129 [Conf]
  19. Thomas Preußer, Steffen Köhler, Rainer G. Spallek
    RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:130-135 [Conf]
  20. Ying Qiao, Luqi
    Admission Control for Dynamic Software Reconfiguration in Systems of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:136-144 [Conf]
  21. J. Willis, A. Gaur, S. Cannon
    An Intelligent Communications Backplane Architecture. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:145-150 [Conf]
  22. Mars Lan, Morteza Biglari-Abhari
    An Adaptive Superscalar Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:151-156 [Conf]
  23. Sebastian Wallner
    A Configurable System-on-Chip Architecture with Descriptors for Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:157-163 [Conf]
  24. Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic
    HiDRA: A New Architecture for Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:164-170 [Conf]
  25. Stephen Bique
    Embedded Software for an Array of Processors. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:171-175 [Conf]
  26. Enoch Hwang
    Building A Custom System-On-A-Chip. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:176-184 [Conf]
  27. Keith S. Vallerio, Niraj K. Jha
    Language Selection for Mobile Systems: Java, C, or Both? [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:185-191 [Conf]
  28. Diarmuid O'Donoghue, James F. Power
    Identifying and Evaluating a Generic Set of Superinstructions for Embedded Java Programs. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:192-198 [Conf]
  29. A-Qun Deng, Huan-Jun Yu, Shang-Xu Hu
    Realization of Platform Based on Java Technology for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:199-205 [Conf]
  30. Sung-Lim Yun, Dong-Keun Nam, Se Man Oh, Jung-Sook Kim
    Virtual Machine Code for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:206-214 [Conf]
  31. Deji Chen, Aloysius K. Mok
    Scheduling Similarity-Constrained Real-Time Tasks. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:215-221 [Conf]
  32. Jason Garbutt, Sabu John, Thurai Vinay
    Embedded Systems for Real-Time Control of Differential Drive WMR. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:222-228 [Conf]
  33. Hyung Jung Kim, Deock Gu Jee, Man Ho Park, Byung Sik Yoon, Song In Choi
    The Real-Time Implementations of AMR Codec for IMT-2000 System. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:229-232 [Conf]
  34. Ye Su, Gurdip Singh
    Synchronization in CAN-Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:233-239 [Conf]
  35. Kyong Hoon Kim, Jong Kim, Sung Je Hong
    Best-Effort Scheduling (m, k)-Firm Real-Time Tasks Based on the (m, k)-Firm Constraint Meeting Probability. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:240-248 [Conf]
  36. Suboh A. Suboh, Nikitas A. Alexandridis, Tarek A. El-Ghazawi
    Performance Analysis Techniques in SOC Design. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:249-255 [Conf]
  37. Jan Traumueller
    Flexible Internet Based Diagnostics of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:256-262 [Conf]
  38. Zille Huma Kamal, Mohammad Ali Salahuddin, Ajay Gupta, Mark Terwilliger, Vijay Bhuse, Benjamin Beckmann
    Analytical Analysis of Data and Decision Fusion in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:263-272 [Conf]
  39. Young Yee, Edward Vidal Jr.
    Embedded Systems for Meteorological Sensor Applications. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:273-279 [Conf]
  40. Achim Ibenthal, Christoph Minkwitz, Mathias Lindner
    Multimedia Architectures of Mobile Phones. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:280-283 [Conf]
  41. R. Athinarayanan, J. N. Dahiya, J. A. Roberts
    A Software Linearization Technique Using Embedded Applications for Measuring Microwave Dielectric Response of Materials. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:284-288 [Conf]
  42. Hyung Jung Kim, Deock Gu Jee, Man Ho Park, Byung Sik Yoon, Song In Choi
    DSP Implementations of 3D Sound System Using HRTF. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:289-292 [Conf]
  43. En-Hsin Huang, Tzilla Elrad
    Intelligent Resource Agents for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:293-302 [Conf]
  44. Scott F. Smith
    A Scalable Coprocessor for Bioinformatic Sequence Alignments. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:303-308 [Conf]
  45. John Robert Burger
    Novel Quantum Computer Emulator Chip. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:309-315 [Conf]
  46. X. Zhang, Gabriel Dragffy, Anthony G. Pipe
    Repair of the Genetic Material in Biologically Inspired Embryonic-Cell-Based Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:316-324 [Conf]
  47. Shahzad Nazar, Behrooz Shirazi, Sungyong Jung
    Performance/Energy Efficiency Analysis of Register Files in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:325-331 [Conf]
  48. Ahmed Sayed, Hussain Al-Asaad
    Survey and Evaluation of Low-Power Full-Adder Cells. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:332-338 [Conf]
  49. S. M. Rezaul Hasan, Nazmul Ula
    A 4GHz Low-Power Folded-Cascode CMOS LC Quadrature VCO for RF Transceivers. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:339-342 [Conf]
  50. Pasquale Corsonello, Stefania Perri, Vitit Kantabutra
    Area- and Power-Reduced Standard-Cell Spanning Tree Adders. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:343-352 [Conf]
  51. Der-Haw Wang, Salam N. Salloum
    Fault-Tolerance Analysis of Some Sorting Networks for Single and Multiple Passes. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:353-359 [Conf]
  52. Jing Zhong, Jon C. Muzio
    An Investigation of Non-Linear Machines as PRPGs in BIST. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:360-366 [Conf]
  53. Bassam Shaer, Kailash Aurangabadkar
    An Automated Algorithm for Partitioning Sequential VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:367-373 [Conf]
  54. Yinhe Han, Xiaowei Li
    Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:374-381 [Conf]
  55. Stephen Bates
    VLSI Issues for the Implementation of 10GBASE-T Ethernet. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:382-386 [Conf]
  56. Nagendra Bhargava Bharatula, Stijn Ossevoort, Paul Lukowicz, Gerhard Tröster
    Reliability Modelling of Embedded System-in-a-Package: Design and Packaging Issues. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:387-392 [Conf]
  57. Hector Arteaga, Hussain Al-Asaad
    Approaches for Monitoring Vectors on Microprocessor Buses. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:393-398 [Conf]
  58. Lubomir Ivanov
    Automatic Extraction of Non-Iterated System Behavior from Verilog Specifications. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:399-406 [Conf]
  59. Scott C. Smith
    Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:407-412 [Conf]
  60. Himanshu Thapliyal, Hamid R. Arabnia
    High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:413-416 [Conf]
  61. James Levy, Jabulani Nyathi
    A High Performance, Low Area Overhead Carry Lookahead Adder. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:417-426 [Conf]
  62. Viktor Bunimov, Manfred Schimmler
    High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and Time. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:427-433 [Conf]
  63. Himanshu Thapliyal, Hamid R. Arabnia
    A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:434-439 [Conf]
  64. Himanshu Thapliyal, Hamid R. Arabnia
    A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:440-446 [Conf]
  65. Scott C. Smith
    Design of a NULL Convention Self-Timed Divider. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:447-453 [Conf]
  66. Jie Long, Robert J. Weber
    A 2.4GHz CMOS Direct Down-Conversion Mixer. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:454-457 [Conf]
  67. Ronald F. DeMara, Amit Kejriwal, Jude Seeber
    Feedback Techniques for Dual-Rail Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:458-464 [Conf]
  68. Kamala Hariharan, Shoba Krishnan, V. P. Gopinath
    Impact of Gate Leakage on the Performance of Analog Integrated Circuits - A Simulation Study. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:465-474 [Conf]
  69. Xin Jia, Ranga Vemuri
    A Design Methodology for Self-Timed Event Logic Pipelines. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:475-479 [Conf]
  70. D. P. Vasudevan, Parag K. Lala
    A New Reversible Logic Gate and its Applications. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:480-484 [Conf]
  71. Kazuya Shinozuka
    A Graph Approach to Two-Level Logic Minimization. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:485-490 [Conf]
  72. P. W. Chandana Prasad, Ali Assi, Mohamed Raseen
    BDD Minimization Using Graph Parameter Permutation. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:491-496 [Conf]
  73. Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji
    A Fast Hierarchical Approach to FPGA Placement. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:497-503 [Conf]
  74. Jong Kang Park, Jong Tae Kim, Myung Chul Shin
    High Performance Single Chip Implementation for a Digital Protective Relay Using FPGA. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:504-508 [Conf]
  75. S. P. Joy Vasantha Rani, P. Kanagasabapathy
    Design of Neural Network on FPGA. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:509-512 [Conf]
  76. Chao-Ming Tseng, Chih-Sheng Chen, Chua-Huang Huang
    Quantum Gates Revisited: A Tensor Product Based Interpretation Model. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:513-522 [Conf]
  77. David J. Betowski, Daniel Dwyer, Valeriu Beiu
    A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:523-529 [Conf]
  78. Andy Widjaja, José G. Delgado-Frias
    An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:530-535 [Conf]
  79. Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
    A Distributed FIFO Scheme for System on Chip Inter-Component Communication. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:536-540 [Conf]
  80. Valeriu Beiu, Mawahib Sulieman
    Optimal Practical Perceptron Addition Application to Single Electron Technology. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:541-550 [Conf]
  81. Howard E. Michel, David Rancour, Sushanth Iringentavida
    CMOS Implementation of Phase-Encoded Complex-Valued Artificial Neural Networks. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:551-557 [Conf]
  82. YunKyung Lee, Sangwoo Lee, Youngsae Kim
    AES Crypto-Processor Design Supporting 128/192/256 Bits Input Key Length for Smart Card. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:558-563 [Conf]
  83. Deng Lei, Wen Gao, Ming-Zeng Hu, Zhenzhou Ji
    An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:564-568 [Conf]
  84. Sang-Woo Lee, Jeong-Nyeo Kim, Jong-Soo Jang
    An Efficient Divider Architecture over GF(2m) for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:569-576 [Conf]
  85. Li-Chuan Weng, Xiaojun Wang, Alan P. Su, Bin Liu
    Low Power Heuristic Block-level Voltage/Frequency Scheduling. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:577-581 [Conf]
  86. Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
    A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:582-588 [Conf]
  87. E. Barteska, Christof Paar, Jan Pelzl, Volker Wittelsberger, Thomas J. Wollinger
    Case Study: Compiler Comparison for an Embedded Cryptographical Application. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:589-595 [Conf]
  88. Suboh A. Suboh, Nikitas A. Alexandridis
    A Computational Intellegence Approach for Parametrized SoC Optimization. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:596-600 [Conf]
  89. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:601-605 [Conf]
  90. Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
    FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:606-610 [Conf]
  91. Kun Huang, Shivakumar Sastry
    Evaluating Communications in a Sensor-Actuator Network for Automation. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:611-617 [Conf]
  92. S. Omar
    Automated Credit Oriented System for Computer Network Administration. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:618-0 [Conf]
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