The SCEAS System
Navigation Menu

Conferences in DBLP

Design Automation Conference (DAC) (dac)
1994 (conf/dac/94)

  1. Pai H. Chou, Gaetano Borriello
    Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:1-4 [Conf]
  2. Ing-Jer Huang, Alvin M. Despain
    Synthesis of Instruction Sets for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:5-11 [Conf]
  3. José C. Monteiro, Srinivas Devadas, Bill Lin
    A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:12-17 [Conf]
  4. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:18-23 [Conf]
  5. Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
    ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:24-30 [Conf]
  6. Edoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli
    Simultaneous Placement and Module Optimization of Analog IC's. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:31-35 [Conf]
  7. Sharad Mehrotra, Paul D. Franzon, Wentai Liu
    Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:36-40 [Conf]
  8. Ajit M. Prabhu
    Management Issues in Eda. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:41-47 [Conf]
  9. Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett
    Executive Perspective and Vision of the Future of EDA (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:48- [Conf]
  10. Gjalt G. de Jong, Bill Lin
    A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:49-55 [Conf]
  11. Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev
    Basic Gate Implementation of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:56-62 [Conf]
  12. Ruchir Puri, Jun Gu
    A Modular Partitioning Approach for Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:63-69 [Conf]
  13. Christian D. Nielsen, Michael Kishinevsky
    Performance Analysis Based on Timing Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:70-76 [Conf]
  14. Pranav Ashar, Sharad Malik
    Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:77-80 [Conf]
  15. Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal
    An Exact Algorithm for Selecting Partial Scan Flip-Flops. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:81-86 [Conf]
  16. Srimat T. Chakradhar, Sujit Dey
    Resynthesis and Retiming for Optimum Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:87-93 [Conf]
  17. Wen-Chang Fang, Sandeep K. Gupta
    Clock Grouping: A Low Cost DFT Methodology for Delay Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:94-99 [Conf]
  18. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Exact Minimum Cycle Times for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:100-105 [Conf]
  19. Elizabeth A. Walkup, Gaetano Borriello
    Interface Timing Verification with Application to Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:106-112 [Conf]
  20. Anurag P. Gupta, Daniel P. Siewiorek
    Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:113-119 [Conf]
  21. Ajay J. Daga, William P. Birmingham
    The Minimization and Decomposition of Interface State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:120-125 [Conf]
  22. Horng-Fei Jyu, Sharad Malik
    Statistical Delay Modeling in Logic Design and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:126-130 [Conf]
  23. Sean Murphy
    Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:131-134 [Conf]
  24. Wojciech Maly
    Cost of Silicon Viewed from VLSI Design Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:135-142 [Conf]
  25. Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabaey
    Memory Estimation for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:143-148 [Conf]
  26. David J. Kolson, Alexandru Nicolau, Nikil D. Dutt
    Minimization of Memory Traffic in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:149-154 [Conf]
  27. Mohammed Aloqeely, C. Y. Roger Chen
    Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:155-160 [Conf]
  28. Dennis S. Fernandez
    Intellectual Property Protection in the EDA Industry. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:161-163 [Conf]
  29. William M. van Cleemput, Ewald Detjens, Herman Beke, George C. Chen, Joseph Hustein, William Lattin, Dennis S. Fernandez
    Software Patents and Their Potential Impact on the EDA Community (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:164- [Conf]
  30. Kai Zhu, D. F. Wong
    Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:165-170 [Conf]
  31. Yachyang Sun, C. L. Liu
    Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:171-176 [Conf]
  32. Ikuo Harada, Hitoshi Kitazawa
    A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:177-181 [Conf]
  33. Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
    A Unified Approach to Multilayer Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:182-187 [Conf]
  34. Geoffrey Bunza, Steve Schulz, Tommy Jansson, Alex Silbey, Steve Ma, Edward H. Frank
    PESDA and Design Abstraction: How High is Up? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:188- [Conf]
  35. Miodrag Potkonjak, Mani B. Srivastava, Anantha Chandrakasan
    Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:189-194 [Conf]
  36. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Clock Period Optimization During Resource Sharing and Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:195-200 [Conf]
  37. Miodrag Potkonjak, Sujit Dey
    Optimizing Resource Utilization and Testability Using Hot Potato Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:201-205 [Conf]
  38. Ian G. Harris, Alex Orailoglu
    Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:206-211 [Conf]
  39. Masahiro Tomita, Tamotsu Yamamoto, Fuminori Sumikawa, Kotaro Hirano
    Rectification of Multiple Logic Design Errors in Multiple Output Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:212-217 [Conf]
  40. Andreas Kuehlmann, David Ihsin Cheng, Arvind Srinivasan, David P. LaPotin
    Error Diagnosis for Transistor-Level Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:218-224 [Conf]
  41. Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
    Heuristic Minimization of BDDs Using Don't Cares. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:225-231 [Conf]
  42. Kai Zhu, D. F. Wong
    Clock Skew Minimization During FPGA Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:232-237 [Conf]
  43. Roman Kuznar, Franc Brglez, Baldomir Zajc
    Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:238-243 [Conf]
  44. Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
    Circuit Partitioning for Huge Logic Emulation Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:244-249 [Conf]
  45. Pravil Gupta, Chih-Tung Chen, J. C. DeSouza-Batista, Alice C. Parker
    Experience with Image Compression Chip Design using Unified System Construction Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:250-256 [Conf]
  46. Wang Tek Kee, Dennis Sng, Jacob Gan, Low Kin Kiong
    The Use of CAD Frameworks in a CIM Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:257-261 [Conf]
  47. Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno
    Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:262-269 [Conf]
  48. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Probabilistic Analysis of Large Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:270-275 [Conf]
  49. Alan J. Hu, Gary York, David L. Dill
    New Techniques for Efficient Verification with Implicitly Conjoined BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:276-282 [Conf]
  50. Adnan Aziz, Serdar Tasiran, Robert K. Brayton
    BDD Variable Ordering for Interacting Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:283-288 [Conf]
  51. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:289-293 [Conf]
  52. Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
    Microprocessor Testing: Which Technique is Best? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:294- [Conf]
  53. Sanko Lan, Avi Ziv, Abbas El Gamal
    Placement and Routing for a Field Programmable Multi-Chip Module. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:295-300 [Conf]
  54. Sudip Nag, Rob A. Rutenbar
    Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:301-307 [Conf]
  55. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
    Layout Driven Logic Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:308-313 [Conf]
  56. Kenneth L. McMillan
    Fitting Formal Methods into the Design Cycle. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:314-319 [Conf]
  57. Ronald Collett, Mike Gianfagna, Michel Courtoy, Martin Baynes, Johan Van Ginderdeuren, Kenneth L. McMillan, Stephen Ricca, Alberto L. Sangiovanni-Vincentelli, Steve Sapiro, Naeem Zafar
    Panel: Complex System Verification: The Challenge Ahead. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:320- [Conf]
  58. Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski
    A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:321-326 [Conf]
  59. Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang
    A Methodology and Algorithms for Post-Placement Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:327-332 [Conf]
  60. Sasan Iman, Massoud Pedram, Kamal Chaudhary
    Technology Mapping Using Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:333-338 [Conf]
  61. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Boolean Matching Using Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:339-344 [Conf]
  62. Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
    Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:345-356 [Conf]
  63. Krishnendu Chakrabarty, John P. Hayes
    DFBT: A Design-for-Testability Method Based on Balance Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:351-357 [Conf]
  64. Irith Pomeranz, Sudhakar M. Reddy
    Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:358-364 [Conf]
  65. Kwang-Ting Cheng, Hsi-Chuan Chen
    Generation of High Quality Non-Robust Tests for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:365-369 [Conf]
  66. Jui-Ching Shyur, Hung-Pin Chen, Tai-Ming Parng
    On Testing Wave Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:370-374 [Conf]
  67. Masato Edahiro
    An Efficient Zero-Skew Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:375-380 [Conf]
  68. Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
    Rectilinear Steiner Trees with Minimum Elmore Delay. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:381-386 [Conf]
  69. Sachin S. Sapatnekar
    RC Interconnect Optimization Under the Elmore Delay Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:387-391 [Conf]
  70. Ashok Vittal, Malgorzata Marek-Sadowska
    Minimal Delay Interconnect Design Using Alphabetic Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:392-396 [Conf]
  71. Qiong Yu, Sandeep Badida, Naveed A. Sherwani
    Algorithmic Aspects of Three Dimensional MCM Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:397-401 [Conf]
  72. Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess
    Routing for Manufacturability. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:402-406 [Conf]
  73. Andrew J. Graham, Richard Goldman, Wen-Tsuen Chen, Kerry Hanson, Nikolay G. Malishev, Shin-ichi Nakayama
    Technology Summit - A View from the Top (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:407- [Conf]
  74. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Optimum Functional Decomposition Using Encoding. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:408-414 [Conf]
  75. Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
    Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:415-419 [Conf]
  76. Shin-ichi Minato
    Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:420-424 [Conf]
  77. Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Optimization Using Exact Sensitization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:425-429 [Conf]
  78. Kazuo Iwama, Kensuke Hino
    Random Generation of Test Instances for Logic Optimizers. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:430-434 [Conf]
  79. Kurt Keutzer
    Hardware-Software Co-Design and ESDA. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:435-436 [Conf]
  80. Asawaree Kalavade, Edward A. Lee
    Manifestations of Heterogeneity in Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:437-438 [Conf]
  81. James A. Rowson
    Hardware/Software Co-Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:439-440 [Conf]
  82. S. C. Prasad, P. Anirudhan, Patrick W. Bosshart
    A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:441-446 [Conf]
  83. Oz Levia, Serge Maginot, Jacques Rouillard
    Lessons in Language Design: Cost/Benefit analysis of VHDL Features. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:447-453 [Conf]
  84. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:454-459 [Conf]
  85. P. H. Kelly, Kevin J. Page, Paul M. Chau
    Rapid Prototyping of ASIC Based Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:460-465 [Conf]
  86. Polen Kission, Hong Ding, Ahmed Amine Jerraya
    Structured Design Methodology for High-Level Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:466-471 [Conf]
  87. Reid A. Baldwin, Moon-Jung Chung
    Design Methodology Management Using Graph Grammars. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:472-478 [Conf]
  88. Ivan P. Radivojevic, Forrest Brewer
    Incorporating Speculative Execution in Exact Control-Dependent Scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:479-484 [Conf]
  89. Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass
    Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:485-490 [Conf]
  90. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:491-496 [Conf]
  91. Maria Domenica Di Benedetto, Pasquale Lucibello, Alberto L. Sangiovanni-Vincentelli, K. Yamaguchi
    Chain Closure: A Problem in Molecular CAD. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:497-502 [Conf]
  92. Patrick C. McGeer, Steven Trimberger, Erik Carlson, Dave Hightower, Ulrich Lauther, Alberto L. Sangiovanni-Vincentelli
    DA Algorithms in Non-EDA Applications: How Universal Are Our Techniques? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:503- [Conf]
  93. Irith Pomeranz, Sudhakar M. Reddy
    On Improving Fault Diagnosis for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:504-509 [Conf]
  94. Takaharu Nagumo, Masahiko Nagai, Takao Nishida, Masayuki Miyoshi, Shunsuke Miyamoto
    VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:510-515 [Conf]
  95. Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
    An Efficient Path Delay Fault Coverage Estimator. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:516-521 [Conf]
  96. Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
    Path Hashing to Accelerate Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:522-526 [Conf]
  97. Kenneth A. Radtke
    The AT&T 5ESS Hardware Design Environment: A Large System's Hardware design Process. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:527-531 [Conf]
  98. Albert E. Casavant
    MIST - A Design Aid for Programmable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:532-536 [Conf]
  99. Hong Shin Jun, Sun Young Hwang
    Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:537-541 [Conf]
  100. Yaw Fann, Minjoong Rim, Rajiv Jain
    Global Scheduling for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:542-546 [Conf]
  101. Sanjiv Narayan, Daniel Gajski
    Protocol Generation for Communication Channels. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:547-551 [Conf]
  102. Ramesh Karri, Alex Orailoglu
    Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:552-556 [Conf]
  103. Lawrence F. Arnstein, Donald E. Thomas
    The Attributed-Behavior Abstraction and Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:557-561 [Conf]
  104. Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura
    Design Reuse: Fact or Fiction? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:562- [Conf]
  105. Andrew B. Kahng, Sudhakar Muddu
    Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:563-569 [Conf]
  106. Vladimir Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director
    MONSTR: A Complete Thermal Simulator of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:570-575 [Conf]
  107. Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
    A Gate-Delay Model for high-Speed CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:576-580 [Conf]
  108. Chung-Jung Chen, Wu-Shiung Feng
    Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:581-585 [Conf]
  109. Thomas F. Fox
    The Design of High-Performance Microprocessors at Digital. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:586-591 [Conf]
  110. Tadahiko Nishimukai
    Hitachi-PA/50, SH Series Microcontroller. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:592-593 [Conf]
  111. Matthias Schöbinger, Tobias G. Noll
    Low Power CMOS Design Strategies. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:594-595 [Conf]
  112. Derek L. Beatty, Randal E. Bryant
    Formally Verifying a Microprocessor Using a Simulation Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:596-602 [Conf]
  113. Vishal Bhagwati, Srinivas Devadas
    Automatic Verification of Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:603-608 [Conf]
  114. Eric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man
    A Time Abstraction Method for Efficient Verification of Communicating Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:609-614 [Conf]
  115. A. S. Krishnakumar, Kwang-Ting Cheng
    On the Computation of the Set of Reachable States of Hybrid Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:615-621 [Conf]
  116. Tuyen V. Nguyen
    Efficient Simulation of Lossy and Dispersive Transmission Lines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:622-627 [Conf]
  117. Monjurul Haque, Ali El-Zein, S. Chowdhury
    A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:628-633 [Conf]
  118. Luis Miguel Silveira, Ibrahim M. Elfadel, Jacob White, Moni Chilukuri, Kenneth S. Kundert
    An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:634-639 [Conf]
  119. Rohini Gupta, Lawrence T. Pillage
    OTTER: Optimal Termination of Transmission Lines Excluding Radiation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:640-645 [Conf]
  120. Bernhard M. Riess, Konrad Doll, Frank M. Johannes
    Partitioning Very Large Circuits Using Analytical Placement Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:646-651 [Conf]
  121. Charles J. Alpert, Andrew B. Kahng
    Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:652-657 [Conf]
  122. Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng
    Data Flow Partitioning for Clock Period and Latency Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:658-663 [Conf]
  123. Thang Nguyen Bui, Byung Ro Moon
    A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:664-669 [Conf]
  124. Jason Cong, Zheng Li, Rajive Bagrodia
    Acyclic Multi-Way Partitioning of Boolean Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:670-675 [Conf]
  125. Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier
    Design Automation Tools for FPGA Design (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:676- [Conf]
  126. Huey-Yih Wang, Robert K. Brayton
    Permissible Observability Relations in FSM Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:677-683 [Conf]
  127. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A Fully Implicit Algorithm for Exact State Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:684-690 [Conf]
  128. Shankar Krishnamoorthy, Frederic Mailhot
    Boolean Matching of Sequential Elements. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:691-697 [Conf]
  129. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
    Sequential Circuit Test Generation in a Genetic Algorithm Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:698-704 [Conf]
  130. João P. Marques Silva, Karem A. Sakallah
    Dynamic Search-Space Pruning Techniques in Path Sensitization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:705-711 [Conf]
  131. Bapiraju Vinnakota, Jason Andrews
    Functional Test Generation for FSMs by Fault Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:712-715 [Conf]
  132. Steven Parkes, Prithviraj Banerjee, Janak H. Patel
    ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:717-721 [Conf]
  133. Peter Dahlgren, Peter Lidén
    Modeling of Intermediate Node States in switch-Level Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:722-727 [Conf]
  134. Michael G. Xakellis, Farid N. Najm
    Statistical Estimation of the Switching Activity in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:728-733 [Conf]
  135. Bhanu Kapoor
    Improving the Accuracy of Circuit Activity Measurement. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:734-739 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002