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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2001 (conf/dac/2001)

  1. Rita Glover, Marc Halpern, Rich Becks, Richard Kubin, Henry Jurgens, Rick Cassidy, Ted Vucurevich
    Panel: The Electronics Industry Supply Chain: Who Will Do What? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:1-2 [Conf]
  2. Dennis Sylvester, Himanshu Kaul
    Future Performance Challenges in Nanometer Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:3-8 [Conf]
  3. Wojciech Maly
    IC Design in High-Cost Nanometer-Technologies Era. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:9-14 [Conf]
  4. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:15-20 [Conf]
  5. Tiberiu Chelcea, Steven M. Nowick
    Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:21-26 [Conf]
  6. Seapahn Meguerdichian, Milenko Drinic, Darko Kirovski
    Latency-Driven Design of Multi-Purpose Systems-On-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:27-30 [Conf]
  7. Jagesh V. Sanghavi, Albert Wang
    Estimation of Speed, Area, and Power of Parameterizable, Soft IP. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:31-34 [Conf]
  8. Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, Robert F. Damiano
    Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:35-40 [Conf]
  9. Maher N. Mneimneh, Fadi A. Aloul, Chris Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin
    Scalable Hybrid Verification of Complex Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:41-46 [Conf]
  10. Alfred Kölbl, James H. Kukula, Robert F. Damiano
    Symbolic RTL Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:47-52 [Conf]
  11. Bulent I. Dervisoglu
    A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:53-58 [Conf]
  12. Wei-Cheng Lai, Kwang-Ting Cheng
    Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:59-64 [Conf]
  13. Kelly A. Ockunzzi, Christos A. Papachristou
    Test Strategies for BIST at the Algorithmic and Register-Transfer Levels. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:65-70 [Conf]
  14. Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
    Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:71-72 [Conf]
  15. Warren Grobman, M. Thompson, R. Wang, C. Yuan, Ruiqi Tian, E. Demircan
    Reticle Enhancement Technology: Implications and Challenges for Physical Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:73-78 [Conf]
  16. Lars Liebmann, Jennifer Lund, Fook-Luen Heng, Ioana Graur
    Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:79-84 [Conf]
  17. Michael L. Rieger, Jeffrey P. Mayhew, Sridhar Panchapakesan
    Layout Design Methodologies for Sub-Wavelength Manufacturing. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:85-88 [Conf]
  18. Franklin M. Schellenberg, Olivier Toublan, Luigi Capodieci, Bob Socha
    Adoption of OPC and the Impact on Design and Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:89-92 [Conf]
  19. Michael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra
    A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:93-96 [Conf]
  20. Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska
    Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:97-102 [Conf]
  21. Alan Mishchenko, Bernd Steinbach, Marek A. Perkowski
    An Algorithm for Bi-Decomposition of Logic Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:103-108 [Conf]
  22. Martin Charles Golumbic, Aviad Mintz, Udi Rotics
    Factoring and Recognition of Read-Once Functions using Cographs and Normality. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:109-114 [Conf]
  23. Valentina Ciriani
    Logic Minimization using Exclusive OR Gates. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:115-120 [Conf]
  24. Jafar Savoj, Behzad Razavi
    Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:121-126 [Conf]
  25. David Goren, Eliyahu Shamsaev, Israel A. Wagner
    A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:127-132 [Conf]
  26. Sree Ganesan, Ranga Vemuri
    Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:133-138 [Conf]
  27. Wim Verhaegen, Georges G. E. Gielen
    Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:139-144 [Conf]
  28. Irith Pomeranz
    Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:145-150 [Conf]
  29. Ismet Bayraktaroglu, Alex Orailoglu
    Test Volume and Application Time Reduction Through Scan Chain Concealment. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:151-155 [Conf]
  30. Irith Pomeranz, Sudhakar M. Reddy
    An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:156-161 [Conf]
  31. Sying-Jyan Wang, Sheng-Nan Chiou
    Generating Efficient Tests for Continuous Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:162-165 [Conf]
  32. Anshuman Chandra, Krishnendu Chakrabarty
    Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:166-169 [Conf]
  33. Gabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake
    Panel: Your Core - My Problem? Integration and Verification of IP. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:170-171 [Conf]
  34. Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh
    A Quick Safari Through the Reconfiguration Jungle. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:172-177 [Conf]
  35. Bill Salefski, Levent Caglar
    Re-Configurable Computing in Wireless. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:178-183 [Conf]
  36. Albert Wang, Earl Killian, Dror E. Maydan, Chris Rowen
    Hardware/Software Instruction Set Configurability for System-on-Chip Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:184-188 [Conf]
  37. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A Practical Methodology for Early Buffer and Wire Resource Allocation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:189-194 [Conf]
  38. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and Exploiting Flexibility in Steiner Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:195-198 [Conf]
  39. Kevin M. Lepak, Irwan Luwandi, Lei He
    Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:199-202 [Conf]
  40. Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
    On Optimum Switch Box Designs for 2-D FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:203-208 [Conf]
  41. Sanjukta Bhanja, N. Ranganathan
    Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:209-214 [Conf]
  42. Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
    A Static Estimation Technique of Power Sensitivity in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:215-219 [Conf]
  43. Amit Sinha, Anantha Chandrakasan
    JouleTrack - A Web Based Tool for Software Energy Profiling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:220-225 [Conf]
  44. Miroslav N. Velev, Randal E. Bryant
    Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:226-231 [Conf]
  45. Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
    Circuit-based Boolean Reasoning. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:232-237 [Conf]
  46. Christoph Scholl, Bernd Becker
    Checking Equivalence for Partial Implementations. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:238-243 [Conf]
  47. Bob Bentley
    Validating the Intel Pentium 4 Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:244-248 [Conf]
  48. Ken Albin
    Nuts and Bolts of Core and SoC Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:249-252 [Conf]
  49. Füsun Özgüner, Duane W. Marhefka, Joanne DeGroat, Bruce Wile, Jennifer Stofer, Lyle Hanrahan
    Teaching Future Verification Engineers: The Forgotten Side of Logic Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:253-255 [Conf]
  50. Torbjörn Grahm, Barry Clark
    SoC Integration of Reusable Baseband Bluetooth IP. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:256-261 [Conf]
  51. Paul T. M. van Zeijl
    One-chip Bluetooth ASIC Challenges. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:262- [Conf]
  52. Michael Theobald, Steven M. Nowick
    Transformations for the Synthesis and Optimization of Asynchronous Distributed Control. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:263-268 [Conf]
  53. Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Speculation Techniques for High Level Synthesis of Control Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:269-272 [Conf]
  54. Kiran Bondalapati
    Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:273-276 [Conf]
  55. Armita Peymandoust, Giovanni De Micheli
    Using Symbolic Algebra in Algorithmic Level DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:277-282 [Conf]
  56. Clayton B. McDonald, Randal E. Bryant
    Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:283-288 [Conf]
  57. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    A New Gate Delay Model for Simultaneous Switching and Its Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:289-294 [Conf]
  58. Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
    Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:295-300 [Conf]
  59. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:301-306 [Conf]
  60. Shih-yu Yang, Christos A. Papachristou, Massood Tabib-Azar
    Improving Bus Test Via IDDT and Boundary Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:307-312 [Conf]
  61. Kaamran Raahemifar, Majid Ahmadi
    Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:313-316 [Conf]
  62. Li Chen, Xiaoliang Bai, Sujit Dey
    Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:317-320 [Conf]
  63. Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
    Panel: (When) Will FPGAs Kill ASICs? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:321-322 [Conf]
  64. Michael W. Beattie, Lawrence T. Pileggi
    Inductance 101: Modeling and Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:323-328 [Conf]
  65. Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
    Inductance 101: Analysis and Design Issues. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:329-334 [Conf]
  66. Michael W. Beattie, Lawrence T. Pileggi
    Modeling Magnetic Coupling for On-Chip Interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:335-340 [Conf]
  67. Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi
    Min/max On-Chip Inductance Models and Delay Metrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:341-346 [Conf]
  68. Catherine H. Gebotys
    Utilizing Memory Bandwidth in DSP Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:347-352 [Conf]
  69. Sathishkumar Udayanarayanan, Chaitali Chakrabarti
    Address Code Generation for Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:353-358 [Conf]
  70. J. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan
    Reducing Memory Requirements of Nested Loops for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:359-364 [Conf]
  71. Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
    Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:365-370 [Conf]
  72. Min Zhao, Sachin S. Sapatnekar
    A New Structural Pattern Matching Algorithm for Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:371-376 [Conf]
  73. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:377-382 [Conf]
  74. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Latency and Latch Count Minimization in Wave Steered Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:383-388 [Conf]
  75. Jason Cong, Michail Romesis
    Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:389-394 [Conf]
  76. Juan Antonio Carballo, Stephen W. Director
    Application of Constraint-Based Heuristics in Collaborative Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:395-400 [Conf]
  77. Franc Brglez, Hemang Lavana
    A Universal Client for Distributed Networked Design and Computing. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:401-406 [Conf]
  78. Darko Kirovski, Milenko Drinic, Miodrag Potkonjak
    Hypermedia-Aided Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:407-412 [Conf]
  79. Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai
    A Framework for Object Oriented Hardware Specification, Verification, and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:413-418 [Conf]
  80. Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang
    Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:419- [Conf]
  81. David G. Chinnery, B. Nikolic, Kurt Keutzer
    Achieving 550Mhz in an ASIC Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:420-425 [Conf]
  82. Gregory A. Northrop, Pong-Fei Lu
    A Semi-Custom Design Flow in High-Performance Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:426-431 [Conf]
  83. Stephen E. Rich, Matthew J. Parker, Jim Schwartz
    Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:432-437 [Conf]
  84. Dongkun Shin, Jihong Kim, Seongsoo Lee
    Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:438-443 [Conf]
  85. Jiong Luo, Niraj K. Jha
    Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:444-449 [Conf]
  86. Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    An Approach to Incremental Design of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:450-455 [Conf]
  87. Zhan Yu, Meng-Lin Yu, Alan N. Willson Jr.
    Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:456-461 [Conf]
  88. Anmol Mathur, Sanjeev Saluja
    Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:462-467 [Conf]
  89. In-Cheol Park, Hyeong-Ju Kang
    Digital Filter Synthesis Based on Minimal Signed Digit Representation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:468-473 [Conf]
  90. Gang Qu
    Publicly Detectable Techniques for the Protection of Virtual Components. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:474-479 [Conf]
  91. Rupak Majumdar, Jennifer L. Wong
    Watermarking of SAT using Combinatorial Isolation Lemmas. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:480-485 [Conf]
  92. Gregory Wolfe, Jennifer L. Wong, Miodrag Potkonjak
    Watermarking Graph Partitioning Solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:486-489 [Conf]
  93. Farinaz Koushanfar, Gang Qu
    Hardware Metering. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:490-493 [Conf]
  94. Phillip Restle
    Technical Visualizations in VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:494-499 [Conf]
  95. Jeff Solomon, Mark Horowitz
    Using Texture Mapping with Mipmapping to Render a VLSI Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:500-505 [Conf]
  96. Marc Najork
    Web-based Algorithm Animation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:506-511 [Conf]
  97. Peter Petrov, Alex Orailoglu
    Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:512-517 [Conf]
  98. Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya
    Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:518-523 [Conf]
  99. Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter W. Glynn, Giovanni De Micheli
    Dynamic Voltage Scaling and Power Management for Portable Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:524-529 [Conf]
  100. Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik
    Chaff: Engineering an Efficient SAT Solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:530-535 [Conf]
  101. Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar
    Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:536-541 [Conf]
  102. Jesse Whittemore, Joonyoung Kim, Karem A. Sakallah
    SATIRE: A New Incremental Satisfiability Engine. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:542-545 [Conf]
  103. Emil Gizdarski, Hideo Fujiwara
    A Framework for Low Complexity Static Learning. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:546-549 [Conf]
  104. Sheldon X.-D. Tan, C.-J. Richard Shi
    Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:550-554 [Conf]
  105. Taku Uchino, Jason Cong
    An Interconnect Energy Model Considering Coupling Effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:555-558 [Conf]
  106. Tsung-Hao Chen, Charlie Chung-Ping Chen
    Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:559-562 [Conf]
  107. Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob White
    Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:563-566 [Conf]
  108. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken
    Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:567-572 [Conf]
  109. Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth
    VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:573-578 [Conf]
  110. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:579-585 [Conf]
  111. Seapahn Meguerdichian, Farinaz Koushanfar, Advait Mogre, Dusan Petranovic, Miodrag Potkonjak
    MetaCores: Design and Optimization Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:585-590 [Conf]
  112. Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
    Panel: Is Nanometer Design Under Control? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:591-592 [Conf]
  113. Leonardo Maria Reyneri, F. Cucinotta, A. Serra, Luciano Lavagno
    A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:593-598 [Conf]
  114. Amit Nandi, Radu Marculescu
    System-Level Power/Performance Analysis for Embedded Systems Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:599-604 [Conf]
  115. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level Software Energy Macro-modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:605-610 [Conf]
  116. Hoon Choi, Byeong-Whee Yun, Yun-Tae Lee, Hyunglae Roh
    Model Checking of S3C2400X Industrial Embedded SOC Product. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:611-616 [Conf]
  117. Julia Dushina, Mike Benjamin, Daniel Geist
    Semi-Formal Test Generation with Genevieve. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:617-622 [Conf]
  118. Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor
    A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:623-628 [Conf]
  119. Alex Doboli, Ranga Vemuri
    Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:629-634 [Conf]
  120. Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
    Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:635-640 [Conf]
  121. Davide Bruni, Alessandro Bogliolo, Luca Benini
    Statistical Design Space Exploration for Application-Specific Unit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:641-646 [Conf]
  122. Murali Kudlugi, Charles Selvidge, Russell Tessier
    Static Scheduling of Multiple Asynchronous Domains For Functional Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:647-652 [Conf]
  123. Tong Xiao, Malgorzata Marek-Sadowska
    Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:653-656 [Conf]
  124. Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    An Advanced Timing Characterization Method Using Mode Dependency. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:657-660 [Conf]
  125. Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
    Fast Statistical Timing Analysis By Probabilistic Event Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:661-666 [Conf]
  126. Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
    Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:667-672 [Conf]
  127. Drew Wingard
    MicroNetwork-Based Integration for SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:673-677 [Conf]
  128. Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh Rao
    On-Chip Communication Architecture for OC-768 Network Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:678-683 [Conf]
  129. William J. Dally, Brian Towles
    Route Packets, Not Wires: On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:684-689 [Conf]
  130. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
    Dynamic Management of Scratch-Pad Memory Space. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:690-695 [Conf]
  131. Margarida F. Jacome, Gustavo de Veciana, Satish Pillai
    Clustered VLIW Architectures with Predicated Switching. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:696-701 [Conf]
  132. Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana
    High-Quality Operation Binding for Clustered VLIW Datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:702-707 [Conf]
  133. Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr
    Fast Bit-True Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:708-713 [Conf]
  134. Hai Zhou, Narendra V. Shenoy, William Nicholls
    Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:714-719 [Conf]
  135. Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
    Driver Modeling and Alignment for Worst-Case Delay Noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:720-725 [Conf]
  136. Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
    False Coupling Interactions in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:726-731 [Conf]
  137. Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:732-737 [Conf]
  138. W. Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:738-743 [Conf]
  139. Jörg Henkel, Haris Lekatsas
    A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:744-749 [Conf]
  140. Youngsoo Shin, Takayasu Sakurai
    Coupling-Driven Bus Design for Low-Power Application-Specific Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:750-753 [Conf]
  141. Clark N. Taylor, Sujit Dey, Yi Zhao
    Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:754-757 [Conf]
  142. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    A True Single-Phase 8-bit Adiabatic Multiplier. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:758-763 [Conf]
  143. Jai-Ming Lin, Yao-Wen Chang
    TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:764-769 [Conf]
  144. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:770-775 [Conf]
  145. Mehmet Can Yildiz, Patrick H. Madden
    Improved Cut Sequences for Partitioning Based Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:776-779 [Conf]
  146. Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
    Timing Driven Placement using Physical Net Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:780-783 [Conf]
  147. Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:784-789 [Conf]
  148. Steven E. Schulz, Georgia Marszalek, Greg Hinckley, Greg Spirakis, Karen Vahtra, John A. Darringer, J. George Janac, Handel H. Jones
    Panel: What Drives EDA Innovation? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:790-791 [Conf]
  149. Mehrdad Nourani, Amir Attarha
    Built-In Self-Test for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:792-797 [Conf]
  150. Kaustav Banerjee, Amit Mehrotra
    Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:798-803 [Conf]
  151. Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob White
    Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:804-809 [Conf]
  152. Daniel Kroening, Wolfgang J. Paul
    Automated Pipeline Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:810-815 [Conf]
  153. Kazuyoshi Kohno, Nobu Matsumoto
    A New Verification Methodology for Complex Pipeline Behavior. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:816-821 [Conf]
  154. Richard Lee, Benjamin Tsien
    Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:822-827 [Conf]
  155. Gang Quan, Xiaobo Hu
    Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:828-833 [Conf]
  156. Qinru Qiu, Qing Wu, Massoud Pedram
    Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:834-839 [Conf]
  157. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi
    Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:840-845 [Conf]
  158. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:846-851 [Conf]
  159. Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake
    Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:852-857 [Conf]
  160. Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich
    Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:858-863 [Conf]
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