Conferences in DBLP
Rita Glover , Marc Halpern , Rich Becks , Richard Kubin , Henry Jurgens , Rick Cassidy , Ted Vucurevich Panel: The Electronics Industry Supply Chain: Who Will Do What? [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Sylvester , Himanshu Kaul Future Performance Challenges in Nanometer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly IC Design in High-Cost Nanometer-Technologies Era. [Citation Graph (0, 0)][DBLP ] Conf ] Kanishka Lahiri , Anand Raghunathan , Ganesh Lakshminarayana LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Tiberiu Chelcea , Steven M. Nowick Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Seapahn Meguerdichian , Milenko Drinic , Darko Kirovski Latency-Driven Design of Multi-Purpose Systems-On-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jagesh V. Sanghavi , Albert Wang Estimation of Speed, Area, and Power of Parameterizable, Soft IP. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Wang , Pei-Hsin Ho , Jiang Long , James H. Kukula , Yunshan Zhu , Hi-Keung Tony Ma , Robert F. Damiano Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines. [Citation Graph (0, 0)][DBLP ] Conf ] Maher N. Mneimneh , Fadi A. Aloul , Chris Weaver , Saugata Chatterjee , Karem A. Sakallah , Todd M. Austin Scalable Hybrid Verification of Complex Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred Kölbl , James H. Kukula , Robert F. Damiano Symbolic RTL Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent I. Dervisoglu A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Cheng Lai , Kwang-Ting Cheng Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Kelly A. Ockunzzi , Christos A. Papachristou Test Strategies for BIST at the Algorithmic and Register-Transfer Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Shishpal Rawat , Ingrid Verbauwhede , Gérard Berry , Ramesh Chandra , Daniel Gajski , Kris Konigsfeld , Patrick Schaumont Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP ] Conf ] Warren Grobman , M. Thompson , R. Wang , C. Yuan , Ruiqi Tian , E. Demircan Reticle Enhancement Technology: Implications and Challenges for Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Liebmann , Jennifer Lund , Fook-Luen Heng , Ioana Graur Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Michael L. Rieger , Jeffrey P. Mayhew , Sridhar Panchapakesan Layout Design Methodologies for Sub-Wavelength Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Franklin M. Schellenberg , Olivier Toublan , Luigi Capodieci , Bob Socha Adoption of OPC and the Impact on Design and Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Sanie , Michel Côté , Philippe Hurat , Vinod Malhotra A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wei Jim Chang , Kai Wang , Malgorzata Marek-Sadowska Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Bernd Steinbach , Marek A. Perkowski An Algorithm for Bi-Decomposition of Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Charles Golumbic , Aviad Mintz , Udi Rotics Factoring and Recognition of Read-Once Functions using Cographs and Normality. [Citation Graph (0, 0)][DBLP ] Conf ] Valentina Ciriani Logic Minimization using Exclusive OR Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Jafar Savoj , Behzad Razavi Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Goren , Eliyahu Shamsaev , Israel A. Wagner A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Sree Ganesan , Ranga Vemuri Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wim Verhaegen , Georges G. E. Gielen Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Alex Orailoglu Test Volume and Application Time Reduction Through Scan Chain Concealment. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Sying-Jyan Wang , Sheng-Nan Chiou Generating Efficient Tests for Continuous Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Anshuman Chandra , Krishnendu Chakrabarty Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Gabe Moretti , Tim Hopes , Ramesh Narayanaswamy , Nanette Collins , Dave Kelf , Tom Anderson , Janick Bergeron , Ashish Dixit , Peter Flake Panel: Your Core - My Problem? Integration and Verification of IP. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Schaumont , Ingrid Verbauwhede , Kurt Keutzer , Majid Sarrafzadeh A Quick Safari Through the Reconfiguration Jungle. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Salefski , Levent Caglar Re-Configurable Computing in Wireless. [Citation Graph (0, 0)][DBLP ] Conf ] Albert Wang , Earl Killian , Dror E. Maydan , Chris Rowen Hardware/Software Instruction Set Configurability for System-on-Chip Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Jiang Hu , Sachin S. Sapatnekar , Paul Villarrubia A Practical Methodology for Early Buffer and Wire Resource Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Elaheh Bozorgzadeh , Ryan Kastner , Majid Sarrafzadeh Creating and Exploiting Flexibility in Steiner Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin M. Lepak , Irwan Luwandi , Lei He Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbing Fan , Jiping Liu , Yu-Liang Wu , Chak-Chung Cheung On Optimum Switch Box Designs for 2-D FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjukta Bhanja , N. Ranganathan Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Taewhan Kim , Ki-Seok Chung , Chien-Liang Liu A Static Estimation Technique of Power Sensitivity in Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Sinha , Anantha Chandrakasan JouleTrack - A Web Based Tool for Software Energy Profiling. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev , Randal E. Bryant Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kuehlmann , Malay K. Ganai , Viresh Paruthi Circuit-based Boolean Reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Scholl , Bernd Becker Checking Equivalence for Partial Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Bentley Validating the Intel Pentium 4 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Albin Nuts and Bolts of Core and SoC Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Füsun Özgüner , Duane W. Marhefka , Joanne DeGroat , Bruce Wile , Jennifer Stofer , Lyle Hanrahan Teaching Future Verification Engineers: The Forgotten Side of Logic Design. [Citation Graph (0, 0)][DBLP ] Conf ] Torbjörn Grahm , Barry Clark SoC Integration of Reusable Baseband Bluetooth IP. [Citation Graph (0, 0)][DBLP ] Conf ] Paul T. M. van Zeijl One-chip Bluetooth ASIC Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Theobald , Steven M. Nowick Transformations for the Synthesis and Optimization of Asynchronous Distributed Control. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Gupta , Nick Savoiu , Sunwoo Kim , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Speculation Techniques for High Level Synthesis of Control Intensive Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Kiran Bondalapati Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching. [Citation Graph (0, 0)][DBLP ] Conf ] Armita Peymandoust , Giovanni De Micheli Using Symbolic Algebra in Algorithmic Level DSP Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Clayton B. McDonald , Randal E. Bryant Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Chi Chen , Sandeep K. Gupta , Melvin A. Breuer A New Gate Delay Model for Simultaneous Switching and Its Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Feng Wu , Chih-Tsun Huang , Kuo-Liang Cheng , Chih-Wea Wang , Cheng-Wen Wu Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-yu Yang , Christos A. Papachristou , Massood Tabib-Azar Improving Bus Test Via IDDT and Boundary Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Kaamran Raahemifar , Majid Ahmadi Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Li Chen , Xiaoliang Bai , Sujit Dey Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , Max Baron , Thomas Daniel , Rajeev Jayaraman , Zvi Or-Bach , Jonathan Rose , Carl Sechen Panel: (When) Will FPGAs Kill ASICs? [Citation Graph (0, 0)][DBLP ] Conf ] Michael W. Beattie , Lawrence T. Pileggi Inductance 101: Modeling and Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao Inductance 101: Analysis and Design Issues. [Citation Graph (0, 0)][DBLP ] Conf ] Michael W. Beattie , Lawrence T. Pileggi Modeling Magnetic Coupling for On-Chip Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Chang Lu , Mustafa Celik , Tak Young , Lawrence T. Pileggi Min/max On-Chip Inductance Models and Delay Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys Utilizing Memory Bandwidth in DSP Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Sathishkumar Udayanarayanan , Chaitali Chakrabarti Address Code Generation for Digital Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] J. Ramanujam , Jinpyo Hong , Mahmut T. Kandemir , Amit Narayan Reducing Memory Requirements of Nested Loops for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Per Gunnar Kjeldsberg , Francky Catthoor , Einar J. Aas Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Min Zhao , Sachin S. Sapatnekar A New Structural Pattern Matching Algorithm for Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Shrirang K. Karandikar , Sachin S. Sapatnekar Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska Latency and Latch Count Minimization in Wave Steered Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Michail Romesis Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Antonio Carballo , Stephen W. Director Application of Constraint-Based Heuristics in Collaborative Design. [Citation Graph (0, 0)][DBLP ] Conf ] Franc Brglez , Hemang Lavana A Universal Client for Distributed Networked Design and Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Milenko Drinic , Miodrag Potkonjak Hypermedia-Aided Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tommy Kuhn , Tobias Oppold , Markus Winterholer , Wolfgang Rosenstiel , Mark Edwards , Yaron Kashai A Framework for Object Oriented Hardware Specification, Verification, and Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Georges G. E. Gielen , Mike Sottak , Mike Murray , Linda Kaye , Maria del Mar Hershenson , Kenneth S. Kundert , Philippe Magarshack , Akria Matsuzawa , Ronald A. Rohrer , Ping Yang Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? [Citation Graph (0, 0)][DBLP ] Conf ] David G. Chinnery , B. Nikolic , Kurt Keutzer Achieving 550Mhz in an ASIC Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory A. Northrop , Pong-Fei Lu A Semi-Custom Design Flow in High-Performance Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen E. Rich , Matthew J. Parker , Jim Schwartz Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkun Shin , Jihong Kim , Seongsoo Lee Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jiong Luo , Niraj K. Jha Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Pop , Petru Eles , Traian Pop , Zebo Peng An Approach to Incremental Design of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zhan Yu , Meng-Lin Yu , Alan N. Willson Jr. Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anmol Mathur , Sanjeev Saluja Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] In-Cheol Park , Hyeong-Ju Kang Digital Filter Synthesis Based on Minimal Signed Digit Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu Publicly Detectable Techniques for the Protection of Virtual Components. [Citation Graph (0, 0)][DBLP ] Conf ] Rupak Majumdar , Jennifer L. Wong Watermarking of SAT using Combinatorial Isolation Lemmas. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory Wolfe , Jennifer L. Wong , Miodrag Potkonjak Watermarking Graph Partitioning Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Farinaz Koushanfar , Gang Qu Hardware Metering. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Restle Technical Visualizations in VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Solomon , Mark Horowitz Using Texture Mapping with Mipmapping to Render a VLSI Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Najork Web-based Algorithm Animation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed Amine Jerraya Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Tajana Simunic , Luca Benini , Andrea Acquaviva , Peter W. Glynn , Giovanni De Micheli Dynamic Voltage Scaling and Power Management for Portable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew W. Moskewicz , Conor F. Madigan , Ying Zhao , Lintao Zhang , Sharad Malik Chaff: Engineering an Efficient SAT Solver. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Anubhav Gupta , Zijiang Yang , Pranav Ashar Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Jesse Whittemore , Joonyoung Kim , Karem A. Sakallah SATIRE: A New Incremental Satisfiability Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Gizdarski , Hideo Fujiwara A Framework for Low Complexity Static Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Sheldon X.-D. Tan , C.-J. Richard Shi Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Taku Uchino , Jason Cong An Interconnect Energy Model Considering Coupling Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Hao Chen , Charlie Chung-Ping Chen Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Daniel , Alberto L. Sangiovanni-Vincentelli , Jacob White Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Ajami , Kaustav Banerjee , Massoud Pedram , Lukas P. P. P. van Ginneken Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Ireneusz Janiszewski , Bernhard Hoppe , Hermann Meuth VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Karri , Kaijie Wu , Piyush Mishra , Yongkook Kim Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP ] Conf ] Seapahn Meguerdichian , Farinaz Koushanfar , Advait Mogre , Dusan Petranovic , Miodrag Potkonjak MetaCores: Design and Optimization Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Bing J. Sheu , Nancy Nettleton , John M. Cohn , Shekhar Borkar , Louis Scheffer , Ed Cheng , Sang Wang Panel: Is Nanometer Design Under Control? [Citation Graph (0, 0)][DBLP ] Conf ] Leonardo Maria Reyneri , F. Cucinotta , A. Serra , Luciano Lavagno A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM . [Citation Graph (0, 0)][DBLP ] Conf ] Amit Nandi , Radu Marculescu System-Level Power/Performance Analysis for Embedded Systems Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tat Kee Tan , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha High-level Software Energy Macro-modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Hoon Choi , Byeong-Whee Yun , Yun-Tae Lee , Hyunglae Roh Model Checking of S3C2400X Industrial Embedded SOC Product. [Citation Graph (0, 0)][DBLP ] Conf ] Julia Dushina , Mike Benjamin , Daniel Geist Semi-Formal Test Generation with Genevieve. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Doboli , Ranga Vemuri Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Kia Bazargan , Seda Ogrenci , Majid Sarrafzadeh Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Bruni , Alessandro Bogliolo , Luca Benini Statistical Design Space Exploration for Application-Specific Unit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Kudlugi , Charles Selvidge , Russell Tessier Static Scheduling of Multiple Asynchronous Domains For Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Xiao , Malgorzata Marek-Sadowska Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Hakan Yalcin , Robert Palermo , Mohammad Mortazavi , Cyrus Bamji , Karem A. Sakallah , John P. Hayes An Advanced Timing Characterization Method Using Mode Dependency. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic Fast Statistical Timing Analysis By Probabilistic Event Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Sgroi , Michael Sheets , Andrew Mihal , Kurt Keutzer , Sharad Malik , Jan M. Rabaey , Alberto L. Sangiovanni-Vincentelli Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. [Citation Graph (0, 0)][DBLP ] Conf ] Drew Wingard MicroNetwork-Based Integration for SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Faraydon Karim , Anh Nguyen , Sujit Dey , Ramesh Rao On-Chip Communication Architecture for OC-768 Network Processors. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Dally , Brian Towles Route Packets, Not Wires: On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , J. Ramanujam , Mary Jane Irwin , Narayanan Vijaykrishnan , Ismail Kadayif , Amisha Parikh Dynamic Management of Scratch-Pad Memory Space. [Citation Graph (0, 0)][DBLP ] Conf ] Margarida F. Jacome , Gustavo de Veciana , Satish Pillai Clustered VLIW Architectures with Predicated Switching. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor S. Lapinskii , Margarida F. Jacome , Gustavo de Veciana High-Quality Operation Binding for Clustered VLIW Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Keding , Martin Coors , Olaf Lüthje , Heinrich Meyr Fast Bit-True Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , Narendra V. Shenoy , William Nicholls Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. [Citation Graph (0, 0)][DBLP ] Conf ] Supamas Sirichotiyakul , David Blaauw , Chanhee Oh , Rafi Levy , Vladimir Zolotov , Jingyan Zuo Driver Modeling and Alignment for Worst-Case Delay Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Arunachalam , Ronald D. Blanton , Lawrence T. Pileggi False Coupling Interactions in Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Wook Kim , Seong-Ook Jung , Prashant Saxena , C. L. Liu , Sung-Mo Kang Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP ] Conf ] W. Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel , Haris Lekatsas A2 BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Takayasu Sakurai Coupling-Driven Bus Design for Low-Power Application-Specific Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Clark N. Taylor , Sujit Dey , Yi Zhao Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Suhwan Kim , Conrad H. Ziesler , Marios C. Papaefthymiou A True Single-Phase 8-bit Adiabatic Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Jai-Ming Lin , Yao-Wen Chang TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Yuchun Ma , Xianlong Hong , Sheqin Dong , Yici Cai , Chung-Kuan Cheng , Jun Gu Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. [Citation Graph (0, 0)][DBLP ] Conf ] Mehmet Can Yildiz , Patrick H. Madden Improved Cut Sequences for Partitioning Based Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Halpin , C. Y. Roger Chen , Naresh Sehgal Timing Driven Placement using Physical Net Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Luca Macchiarulo , Alberto Macii , Enrico Macii , Massimo Poncino From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Steven E. Schulz , Georgia Marszalek , Greg Hinckley , Greg Spirakis , Karen Vahtra , John A. Darringer , J. George Janac , Handel H. Jones Panel: What Drives EDA Innovation? [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , Amir Attarha Built-In Self-Test for Signal Integrity. [Citation Graph (0, 0)][DBLP ] Conf ] Kaustav Banerjee , Amit Mehrotra Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Yehia Massoud , Jamil Kawa , Don MacMillen , Jacob White Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Kroening , Wolfgang J. Paul Automated Pipeline Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuyoshi Kohno , Nobu Matsumoto A New Verification Methodology for Complex Pipeline Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Lee , Benjamin Tsien Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Quan , Xiaobo Hu Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Qinru Qiu , Qing Wu , Massoud Pedram Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service. [Citation Graph (0, 0)][DBLP ] Conf ] Jinfeng Liu , Pai H. Chou , Nader Bagherzadeh , Fadi J. Kurdahi Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rongtian Zhang , Kaushik Roy , Cheng-Kok Koh , David B. Janes Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Seungbae Lee , Gi-Joon Nam , Junseok Chae , Hanseup Kim , Alan J. Drake Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Schenkel , Michael Pronath , Stephan Zizala , Robert Schwencker , Helmut E. Graeb , Kurt Antreich Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. [Citation Graph (0, 0)][DBLP ] Conf ] 