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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2005 (conf/dac/2005)

  1. Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy
    Differentiate and deliver: leveraging your partners. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:1- [Conf]
  2. Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang
    Logic soft errors in sub-65nm technologies design and CAD challenges. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:2-4 [Conf]
  3. William Heidergott
    SEU tolerant device, circuit and processor design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:5-10 [Conf]
  4. Diana Marculescu, Emil Talpes
    Variability and energy awareness: a microarchitecture-level perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:11-16 [Conf]
  5. Peter Petrov, Daniel Tracy, Alex Orailoglu
    Energy-effcient physically tagged caches for embedded processors with virtual memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:17-22 [Conf]
  6. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Hybrid simulation for embedded software energy estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:23-26 [Conf]
  7. Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede
    Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:27-30 [Conf]
  8. Feng Gao, John P. Hayes
    Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:31-36 [Conf]
  9. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    An effective power mode transition technique in MTCMOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:37-42 [Conf]
  10. Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri
    A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:43-46 [Conf]
  11. Lin Yuan, Gang Qu
    Enhanced leakage reduction Technique by gate replacement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:47-50 [Conf]
  12. Ning Dong, Jaijeet S. Roychowdhury
    Automated nonlinear Macromodelling of output buffers for high-speed digital applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:51-56 [Conf]
  13. Ying Wei, Alex Doboli
    Systematic development of analog circuit structural macromodels through behavioral model decoupling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:57-62 [Conf]
  14. Mengmeng Ding, Ranga Vemuri
    A combined feasibility and performance macromodel for analog circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:63-68 [Conf]
  15. Francine Bacchini, David Maliniak, Terry Doherty, Peter McShane, Suhas A. Pai, Sriram Sundararajan, Soo-Kwan Eo, Pascal Urard
    ESL: building the bridge between systems to silicon. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:69-70 [Conf]
  16. Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah
    Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:71-76 [Conf]
  17. Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma
    Correlation-aware statistical timing analysis with non-gaussian delay distributions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:77-82 [Conf]
  18. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
    Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:83-88 [Conf]
  19. Vishal Khandelwal, Ankur Srivastava
    A general framework for accurate statistical timing analysis considering correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:89-94 [Conf]
  20. Feihui Li, Mahmut T. Kandemir
    Locality-conscious workload assignment for array-based computations in MPSOC architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:95-100 [Conf]
  21. Stefan Valentin Gheorghita, Sander Stuijk, Twan Basten, Henk Corporaal
    Automatic scenario detection for improved WCET estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:101-104 [Conf]
  22. Jungeun Kim, Taewhan Kim
    Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:105-110 [Conf]
  23. Ravindra Jejurikar, Rajesh K. Gupta
    Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:111-116 [Conf]
  24. Erik H. Volkerink, Subhasish Mitra
    Response compaction with any number of unknowns using a new LFSR architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:117-122 [Conf]
  25. Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
    Multi-frequency wrapper design and optimization for embedded cores under average power constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:123-128 [Conf]
  26. Irith Pomeranz
    N-detection under transparent-scan. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:129-134 [Conf]
  27. Bo Yang, Kaijie Wu, Ramesh Karri
    Secure scan: a design-for-test architecture for crypto chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:135-140 [Conf]
  28. Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
    A green function-based parasitic extraction method for inhomogeneous substrate layers. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:141-146 [Conf]
  29. Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel
    Analysis of full-wave conductor system impedance over substrate using novel integration techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:147-152 [Conf]
  30. Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter
    Spatially distributed 3D circuit models. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:153-158 [Conf]
  31. Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala
    DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:159-162 [Conf]
  32. Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen
    ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:163-166 [Conf]
  33. Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris
    Choosing flows and methodologies for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:167- [Conf]
  34. Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan
    DFM rules! [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:168-169 [Conf]
  35. Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Partitioning-based approach to fast on-chip decap budgeting and minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:170-175 [Conf]
  36. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:176-181 [Conf]
  37. Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
    Minimizing peak current via opposite-phase clock tree. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:182-185 [Conf]
  38. Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter
    A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:186-189 [Conf]
  39. Chong Zhao, Yi Zhao, Sujit Dey
    Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:190-195 [Conf]
  40. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik
    Temperature-aware resource allocation and binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:196-201 [Conf]
  41. Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee
    Leakage power optimization with dual-Vth library in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:202-207 [Conf]
  42. Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
    Incremental exploration of the combined physical and behavioral design space. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:208-213 [Conf]
  43. M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
    Sign bit reduction encoding for low power applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:214-217 [Conf]
  44. Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga
    A watermarking system for IP protection by a post layout incremental router. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:218-221 [Conf]
  45. Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:222-227 [Conf]
  46. Kris Tiri, Ingrid Verbauwhede
    Simulation models for side-channel information leaks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:228-233 [Conf]
  47. Young H. Cho, William H. Mangione-Smith
    A pattern matching coprocessor for network security. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:234-239 [Conf]
  48. Tomás Balderas-Contreras, René Cumplido
    High performance encryption cores for 3G networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:240-243 [Conf]
  49. Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Efficient fingerprint-based user authentication for embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:244-247 [Conf]
  50. Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi
    Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:248-253 [Conf]
  51. Christian Sauer, Matthias Gries, Sören Sonntag
    Modular domain-specific implementation and exploration framework for embedded software platforms. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:254-259 [Conf]
  52. Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
    Simulation based deadlock analysis for system level designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:260-265 [Conf]
  53. Sorin Manolache, Petru Eles, Zebo Peng
    Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:266-269 [Conf]
  54. Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian
    High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:270-273 [Conf]
  55. Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim
    How to determine the necessity for emerging solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:274-275 [Conf]
  56. David G. Chinnery, Kurt Keutzer
    Closing the power gap between ASIC and custom: an ASIC perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:275-280 [Conf]
  57. Andrew Chang, William J. Dally
    Explaining the gap between ASIC and custom power: a custom perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:281-284 [Conf]
  58. Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
    Keeping hot chips cool. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:285-288 [Conf]
  59. Navraj Nandra, Phil Dworsky, Rick Merritt, John F. D'Ambrosia, Adam Healey, Boris Litinsky, John Stonick, Joe Abler
    Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?". [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:289-290 [Conf]
  60. Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic
    Design methodology for wireless nodes with printed antennas. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:291-296 [Conf]
  61. Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner
    MP core: algorithm and design techniques for efficient channel estimation in wireless applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:297-302 [Conf]
  62. Wolfgang Eberle, Bruno Bougard, Sofie Pollin, Francky Catthoor
    From myth to methodology: cross-layer design for energy-efficient wireless communication. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:303-308 [Conf]
  63. Murari Mani, Anirudh Devgan, Michael Orshansky
    An efficient algorithm for statistical minimization of total power under timing yield constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:309-314 [Conf]
  64. Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar
    Robust gate sizing by geometric programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:315-320 [Conf]
  65. Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov
    Circuit optimization using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:321-324 [Conf]
  66. Bor-Yiing Su, Yao-Wen Chang
    An exact jumper insertion algorithm for antenna effect avoidance/fixing. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:325-328 [Conf]
  67. Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Fine-grained application source code profiling for ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:329-334 [Conf]
  68. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:335-340 [Conf]
  69. Ho Young Kim, Tag Gon Kim
    Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:341-344 [Conf]
  70. Dohyung Kim, Youngmin Yi, Soonhoi Ha
    Trace-driven HW/SW cosimulation using virtual synchronization technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:345-348 [Conf]
  71. Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse
    The Titanic: what went wrong! [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:349-350 [Conf]
  72. Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt
    Wireless platforms: GOPS for cents and MilliWatts. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:351-352 [Conf]
  73. V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
    Design methodology for IC manufacturability based on regular logic-bricks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:353-358 [Conf]
  74. Jie Yang, Luigi Capodieci, Dennis Sylvester
    Advanced timing analysis based on post-OPC extraction of critical dimensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:359-364 [Conf]
  75. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:365-368 [Conf]
  76. Joydeep Mitra, Peng Yu, David Zhigang Pan
    RADAR: RET-aware detailed routing using fast lithography simulations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:369-372 [Conf]
  77. Tsutomu Sasao, Munehiro Matsuura
    BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:373-378 [Conf]
  78. Afshin Abdollahi, Massoud Pedram
    A new canonical form for fast boolean matching in logic synthesis and verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:379-384 [Conf]
  79. Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
    Effective bounding techniques for solving unate and binate covering problems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:385-390 [Conf]
  80. Yayun Wan, Jaijeet S. Roychowdhury
    Operator-based model-order reduction of linear periodically time-varying systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:391-396 [Conf]
  81. V. Vasudevan
    Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:397-402 [Conf]
  82. Saurabh K. Tiwary, Rob A. Rutenbar
    Scalable trajectory methods for on-demand analog macromodel extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:403-408 [Conf]
  83. William Krenik, Anuj Batra
    Cognitive radio techniques for wide area networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:409-412 [Conf]
  84. Jeffrey M. Gilbert, Won-Joon Choi, Qinfang Sun
    MIMO technology for advanced wireless local area networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:413-415 [Conf]
  85. Clark T.-C. Nguyen
    RF MEMS in wireless architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:416-420 [Conf]
  86. Paul Metzgen, Dominic Nancekievill
    Multiplexer restructuring for FPGA implementation cost reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:421-426 [Conf]
  87. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
    FPGA technology mapping: a study of optimality. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:427-432 [Conf]
  88. Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
    Incremental retiming for FPGA physical synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:433-438 [Conf]
  89. Kenneth Eguro, Scott Hauck, Akshay Sharma
    Architecture-adaptive range limit windowing for simulated annealing FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:439-444 [Conf]
  90. Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke
    Word level predicate abstraction and refinement for verifying RTL verilog. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:445-450 [Conf]
  91. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
    Structural search for RTL with predicate learning. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:451-456 [Conf]
  92. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Normalization at the arithmetic bit level. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:457-462 [Conf]
  93. Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman
    Exploiting suspected redundancy without proving it. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:463-466 [Conf]
  94. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
    Multi-threaded reachability. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:467-470 [Conf]
  95. Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel
    Automatic generation of customized discrete fourier transform IPs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:471-474 [Conf]
  96. Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
    Race-condition-aware clock skew scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:475-478 [Conf]
  97. Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel synthesis approach for active leakage power reduction using dynamic supply gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:479-484 [Conf]
  98. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing logic circuits for probabilistic computation in the presence of noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:485-490 [Conf]
  99. Peggy B. McGee, Steven M. Nowick
    A lattice-based framework for the classification and design of asynchronous pipelines. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:491-496 [Conf]
  100. King Ho Tam, Lei He
    Power optimal dual-Vdd buffered tree considering buffer stations and blockages. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:497-502 [Conf]
  101. Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar
    Net weighting to reduce repeater counts during placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:503-508 [Conf]
  102. Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Path based buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:509-514 [Conf]
  103. Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
    Diffusion-based placement migration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:515-520 [Conf]
  104. Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso
    Is methodology the highway out of verification hell? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:521-522 [Conf]
  105. Hongliang Chang, Sachin S. Sapatnekar
    Full-chip analysis of leakage power under process variations, including spatial correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:523-528 [Conf]
  106. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-aware low-power design with voltage scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:529-534 [Conf]
  107. Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director
    Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:535-540 [Conf]
  108. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
    Leakage minimization of nano-scale circuits in the presence of systematic and random variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:541-546 [Conf]
  109. Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta
    A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3). [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:547-548 [Conf]
  110. Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko
    A design platform for 90-nm leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:549-550 [Conf]
  111. Arun Natarajan, Abbas Komijani, Ali Hajimiri
    A 24 GHz phased-array transmitter in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:551-552 [Conf]
  112. Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
    Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:553-558 [Conf]
  113. Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das
    A low latency router supporting adaptivity for on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:559-564 [Conf]
  114. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    Floorplan-aware automated synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:565-570 [Conf]
  115. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:571-574 [Conf]
  116. Sven Heithecker, Rolf Ernst
    Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:575-578 [Conf]
  117. Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar
    Microarchitecture-aware floorplanning using a statistical design of experiments approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:579-584 [Conf]
  118. Zhong Xiu, Rob A. Rutenbar
    Timing-driven placement by grid-warping. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:585-591 [Conf]
  119. Ulrich Brenner, Markus Struzyna
    Faster and better global placement by a new transportation algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:591-596 [Conf]
  120. Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen
    Multilevel full-chip routing for the X-based architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:597-602 [Conf]
  121. David P. Magee
    Matlab extensions for the development, testing and verification of real-time DSP software. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:603-606 [Conf]
  122. Tejas M. Bhatt, Dennis McCain
    Matlab as a development environment for FPGA design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:607-610 [Conf]
  123. Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski
    Should our power approach be current? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:611- [Conf]
  124. Ali Iranli, Massoud Pedram
    DTM: dynamic tone mapping for backlight scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:612-617 [Conf]
  125. Dexin Li, Pai H. Chou
    Application/architecture power co-optimization for embedded systems powered by renewable sources. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:618-623 [Conf]
  126. Le Yan, Lin Zhong, Niraj K. Jha
    User-perceived latency driven voltage scaling for interactive applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:624-627 [Conf]
  127. Jianli Zhuo, Chaitali Chakrabarti
    System-level energy-efficient dynamic task scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:628-631 [Conf]
  128. Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi
    OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:632-637 [Conf]
  129. Jihong Ren, Mark R. Greenstreet
    A unified optimization framework for equalization filter synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:638-643 [Conf]
  130. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi
    Template-driven parasitic-aware optimization of analog integrated circuit layouts. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:644-647 [Conf]
  131. Arthur Nieuwoudt, Yehia Massoud
    Multi-level approach for integrated spiral inductor optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:648-651 [Conf]
  132. Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
    Statistical static timing analysis: how simple can we get? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:652-657 [Conf]
  133. Yu Cao, Lawrence T. Clark
    Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:658-663 [Conf]
  134. Peng Li
    Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:664-669 [Conf]
  135. Yaron Wolfsthal, Rebecca M. Gott
    Formal verification: is it real enough? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:670-671 [Conf]
  136. Umberto Rossi
    Can we really do without the support of formal methods in the verification of large designs? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:672-673 [Conf]
  137. Prosenjit Chatterjee
    Streamline verification process with formal property verification to meet highly compressed design cycle. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:674-677 [Conf]
  138. Seraj Ahmad, Rabi N. Mahapatra
    TCAM enabled on-chip logic minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:678-683 [Conf]
  139. Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
    Hardware speech recognition for user interfaces in low cost, low power devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:684-689 [Conf]
  140. Guangyu Chen, Mahmut T. Kandemir
    Improving java virtual machine reliability for memory-constrained embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:690-695 [Conf]
  141. Corey Goldfeder
    Frequency-based code placement for embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:696-699 [Conf]
  142. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Power emulation: a new paradigm for power estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:700-705 [Conf]
  143. John Wei, Chris Rowen
    Implementing low-power configurable processors: practical options and tradeoffs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:706-711 [Conf]
  144. Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
    Low power network processor design using clock gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:712-715 [Conf]
  145. Nikhil Jayakumar, Sunil P. Khatri
    A variation tolerant subthreshold design approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:716-719 [Conf]
  146. Yan Lin, Lei He
    Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:720-725 [Conf]
  147. Marvin Tom, Guy G. Lemieux
    Logic block clustering of large designs for channel-width constrained FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:726-731 [Conf]
  148. Antonio Carlos Schneider Beck, Luigi Carro
    Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:732-737 [Conf]
  149. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    Beyond safety: customized SAT-based model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:738-743 [Conf]
  150. Domagoj Babic, Jesse D. Bingham, Alan J. Hu
    Efficient SAT solving: beyond supercubes. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:744-749 [Conf]
  151. HoonSang Jin, Fabio Somenzi
    Prime clauses for fast enumeration of satisfying assignments to boolean circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:750-753 [Conf]
  152. Liang Zhang, Mukul R. Prasad, Michael S. Hsiao, Thomas Sidle
    Dynamic abstraction using SAT-based BMC. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:754-757 [Conf]
  153. N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill
    BEOL variability and impact on RC extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:758-759 [Conf]
  154. Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara
    An effective DFM strategy requires accurate process and IP pre-characterization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:760-761 [Conf]
  155. James Tschanz, Keith A. Bowman, Vivek De
    Variation-tolerant circuits: circuit solutions and techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:762-763 [Conf]
  156. Farid N. Najm
    On the need for statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:764-765 [Conf]
  157. David Blaauw, Kaviraj Chopra
    CAD tools for variation tolerance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:766- [Conf]
  158. Matt Nowak, Riko Radojcic
    Are there economic benefits in DFM? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:767-768 [Conf]
  159. Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet
    A generic micro-architectural test plan approach for microprocessor verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:769-774 [Conf]
  160. Sudheendra Hangal, Naveen Chandra, Sridhar Narayanan, Sandeep Chakravorty
    IODINE: a tool to automatically infer dynamic invariants for hardware designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:775-778 [Conf]
  161. Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy
    VLIW: a case study of parallelism verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:779-782 [Conf]
  162. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    StressTest: an automatic approach to test generation via activity monitors. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:783-788 [Conf]
  163. Sadik Ezer, Scott Johnson
    Smart diagnostics for configurable processor verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:789-794 [Conf]
  164. Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang
    Power-aware placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:795-800 [Conf]
  165. Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin
    How accurately can we model timing in a placement engine? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:801-806 [Conf]
  166. Hiran Tennakoon, Carl Sechen
    Efficient and accurate gate sizing with piecewise convex delay models. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:807-812 [Conf]
  167. Yuantao Peng, Xun Liu
    Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:813-818 [Conf]
  168. Marc Geilen, Twan Basten, Sander Stuijk
    Minimising buffer requirements of synchronous dataflow graphs with model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:819-824 [Conf]
  169. Fei Su, Krishnendu Chakrabarty
    Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:825-830 [Conf]
  170. Jianwen Zhu
    Towards scalable flow and context sensitive pointer analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:831-836 [Conf]
  171. Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
    MiniBit: bit-width optimization via affine arithmetic. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:837-840 [Conf]
  172. Bin Wu, Jianwen Zhu, Farid N. Najm
    A non-parametric approach for dynamic range estimation of nonlinear systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:841-844 [Conf]
  173. Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
    Path delay test compaction with process variation tolerance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:845-850 [Conf]
  174. Rasit Onur Topaloglu, Alex Orailoglu
    A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:851-856 [Conf]
  175. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:857-862 [Conf]
  176. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Asynchronous circuits transient faults sensitivity evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:863-868 [Conf]
  177. Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
    Deterministic approaches to analog performance space exploration (PSE). [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:869-874 [Conf]
  178. Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli
    Mixed signal design space exploration through analog platforms. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:875-880 [Conf]
  179. Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert
    Performance space modeling for hierarchical synthesis of analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:881-886 [Conf]
  180. Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano
    Structured/platform ASIC apprentices: which platform will survive your board room? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:887-888 [Conf]
  181. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:889-894 [Conf]
  182. Yongseok Choi, Naehyuck Chang, Taewhan Kim
    DC-DC converter-aware power management for battery-operated embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:895-900 [Conf]
  183. Ravishankar Rao, Sarma B. K. Vrudhula
    Energy optimal speed control of devices with discrete speed sets. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:901-904 [Conf]
  184. Yan Zhang, Zhijian Lu, John Lach, Kevin Skadron, Mircea R. Stan
    Optimal procrastinating voltage scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:905-908 [Conf]
  185. Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak
    Flexible ASIC: shared masking for multiple media processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:909-914 [Conf]
  186. Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
    Device and architecture co-optimization for FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:915-920 [Conf]
  187. Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring technology alternatives for nano-scale FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:921-926 [Conf]
  188. Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
    Piece-wise approximations of RLCK circuit responses using moment matching. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:927-932 [Conf]
  189. Kin Cheong Sou, Alexandre Megretski, Luca Daniel
    A quasi-convex optimization approach to parameterized model order reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:933-938 [Conf]
  190. Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas
    Structure preserving reduction of frequency-dependent interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:939-942 [Conf]
  191. Thomas J. Klemas, Luca Daniel, Jacob K. White
    Segregation by primary phase factors: a full-wave algorithm for model order reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:943-946 [Conf]
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