Conferences in DBLP
Moshe Gavrielov , Richard Goering , Lucio Lanza , Vishal Saluja , Jay Vleeschhouwer Wall street evaluates EDA. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Wirthlin , Brian McMurtrey IP delivery for FPGAs using Applets and JHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Seapahn Megerian , Milenko Drinic , Miodrag Potkonjak Watermarking integer linear programming solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrice Bernardi , Jean François Santucci Model design using hierarchical web-based libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Milenko Drinic , Darko Kirovski Behavioral synthesis via engineering change. [Citation Graph (0, 0)][DBLP ] Conf ] Achim Nohl , Gunnar Braun , Oliver Schliebusch , Rainer Leupers , Heinrich Meyr , Andreas Hoffmann A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Roman L. Lysecky , Susan Cotterell , Frank Vahid A fast on-chip profiler memory. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Jörg Henkel , Venkata Jakkula Design of an one-cycle decompression hardware for performance increase in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Q. Su , Venkataramanan Balakrishnan , Cheng-Kok Koh A factorization-based framework for passivity-preserving model reduction of RLC systems. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Daniel , Joel R. Phillips Model order reduction for strictly passive and causal distributed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joel R. Phillips , Luca Daniel , Luis Miguel Silveira Guaranteed passive balancing transformations for model order reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoliang Bai , Chandramouli Visweswariah , Philip N. Strenski Uncertainty-aware circuit optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Su , Jiang Hu , Sachin S. Sapatnekar , Sani R. Nassif Congestion-driven codesign of power and signal networks. [Citation Graph (0, 0)][DBLP ] Conf ] PariVallal Kannan , Shankar Balachandran , Dinesh Bhatia On metrics for comparing routability estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Ronald Collett , Patrick Groeneveld , Lavi Lev , Nancy Nettleton , Paul K. Rodman , Lambert van den Hoven Tools or users: which is the bigger bottleneck? [Citation Graph (0, 0)][DBLP ] Conf ] George Sery , Shekhar Borkar , Vivek De Life is CMOS: why chase the life after? [Citation Graph (0, 0)][DBLP ] Conf ] H. Bernhard Pogge The next chip challenge: effective methods for viable mixed technology SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian M. Ionescu , Michel J. Declercq , Santanu Mahapatra , Kaustav Banerjee , Jacques Gautier Few electron devices: towards hybrid CMOS-SET integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] R. Martel , V. Derycke , J. Appenzeller , S. Wind , Ph. Avouris Carbon nanotube field-effect transistors and logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Bertacco , Kunle Olukotun Efficient state representation for symbolic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred Kölbl , James H. Kukula , Kurt Antreich , Robert F. Damiano Handling special constructs in symbolic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hazelhurst , Osnat Weissberg , Gila Kamhi , Limor Fix A hybrid verification approach: getting deep into the design. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati , Stefano Quer Can BDDs compete with SAT solvers on bounded model checking? [Citation Graph (0, 0)][DBLP ] Conf ] Luc Séméria , Renu Mehra , Barry M. Pangrle , Arjuna Ekanayake , Andrew Seawright , Daniel Ng RTL c-based methodology for designing and verifying a multi-threaded processor. [Citation Graph (0, 0)][DBLP ] Conf ] Marcio T. Oliveira , Alan J. Hu High-Level specification and automatic generation of IP interface monitors. [Citation Graph (0, 0)][DBLP ] Conf ] Kerstin Eder , Geoff Barrett Achieving maximum performance: a method for the verification of interlocked pipeline control logic. [Citation Graph (0, 0)][DBLP ] Conf ] Arindam Chakrabarti , Pallab Dasgupta , P. P. Chakrabarti , Ansuman Banerjee Formal verification of module interfaces against real time specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay J. Daga , Loa Mize , Subramanyam Sripada , Chris Wolff , Qiuyang Wu Automated timing model generation. [Citation Graph (0, 0)][DBLP ] Conf ] Cho W. Moon , Harish Kriplani , Krishna P. Belkhale Timing model extraction of hierarchical blocks by graph reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Foltin , Brian Foutz , Sean Tyler Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Higuchi An implication-based method to detect multi-cycle paths in large sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sungmee Park , Kenneth Mackenzie , Sundaresan Jayaraman The wearable motherboard: a framework for personalized mobile information processing (PMIP). [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Radu Marculescu , Pradeep K. Khosla Challenges and opportunities in electronic textiles modeling and optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Brunoli , Masao Hotta , Felicia James , Rudy Koch , Roy McGuffin , Andrew J. Moore Analog intellectual property: now? Or never? [Citation Graph (0, 0)][DBLP ] Conf ] Yumin Zhang , Xiaobo Hu , Danny Z. Chen Task scheduling and voltage selection for energy minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula , Chaitali Chakrabarti Battery-conscious task sequencing for portable devices including voltage/clock scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Ismail Kadayif , Mahmut T. Kandemir , Mustafa Karaköy An energy saving strategy based on adaptive loop parallelization. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Robert K. Brayton River PLAs: a regular circuit structure. [Citation Graph (0, 0)][DBLP ] Conf ] Junhyung Um , Taewhan Kim Layout-aware synthesis of arithmetic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Victor De La Luz , Mahmut T. Kandemir , Ibrahim Kolcu Automatic data migration for reducing energy consumption in multi-bank memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , J. Ramanujam , Alok N. Choudhary Exploiting shared scratch pad memory space in embedded multiprocessor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yoonseo Choi , Taewhan Kim Address assignment combined with scheduling in DSP code generation. [Citation Graph (0, 0)][DBLP ] Conf ] Edward H. Sargent Multifunctional photonic integration for the agile optical internet. [Citation Graph (0, 0)][DBLP ] Conf ] James G. Maloney , Brian E. Brewington , Curtis R. Menyuk Computer aided design of long-haul optical transmission systems. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy P. Kurzweg , Steven P. Levitan , Jose A. Martinez , Mark Kahrs , Donald M. Chiarulli A fast optical propagation technique for modeling micro-optical systems. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Brodersen , Anthony M. Hill , John Kibarian , Desmond Kirkpatrick , Mark A. Lavin , Mitsumasa Koyanagi Nanometer design: what hurts next...? [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Xiaoming Yu , Elizabeth M. Rudnick Low-cost sequential ATPG with clock-control DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski , Sanjay Patel , Gregory A. Maston Effective diagnostics through interval unloads in a BIST environment. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sandip Kundu , Sudhakar M. Reddy On output response compression in the presence of unknown output values. [Citation Graph (0, 0)][DBLP ] Conf ] Li Chen , Sujit Dey Software-based diagnosis for processors. [Citation Graph (0, 0)][DBLP ] Conf ] Xun Liu , Marios C. Papaefthymiou Design of a high-throughput low-power IS95 Viterbi decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Ragan , Peter Sandborn , Paul Stoaks A detailed cost model for concurrent use with hardware/software co-design. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunok Oh , Soonhoi Ha Efficient code synthesis from extended dataflow graphs for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ingo Sander , Axel Jantsch Transformation based communication and clock domain refinement for system design. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Richter , Dirk Ziegenbein , Marek Jersak , Rolf Ernst Model composition for scheduling analysis in platform design. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-Yeol Lee , In-Cheol Park Timed compiled-code simulation of embedded software for performance analysis of SOC design. [Citation Graph (0, 0)][DBLP ] Conf ] Simon Jolly , Atanas N. Parashkevov , Tim McDougall Automated equivalence checking of switch level circuits . [Citation Graph (0, 0)][DBLP ] Conf ] Demos Anastasakis , Robert F. Damiano , Hi-Keung Tony Ma , Ted Stanion A practical and efficient method for compare-point matching. [Citation Graph (0, 0)][DBLP ] Conf ] Ying-Tsai Chang , Kwang-Ting Cheng Self-referential verification of gate-level implementations of arithmetic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Santarini , Sudhakar Jilla , Mark Miller , Tommy Eng , Sandeep Khanna , Kamalesh N. Ruparel , Tom Russell , Kazu Yamada Whither (or wither?) ASIC handoff? [Citation Graph (0, 0)][DBLP ] Conf ] Yunjian Jiang , Robert K. Brayton Software synthesis from synchronous specifications using logic simulation techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Armita Peymandoust , Giovanni De Micheli , Tajana Simunic Complex library mapping for embedded software using symbolic algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Maghsoud Abbaspour , Jianwen Zhu Retargetable binary utilities. [Citation Graph (0, 0)][DBLP ] Conf ] Zhining Huang , Sharad Malik Exploiting operation level parallelism through dynamically reconfigurable datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Edson L. Horta , John W. Lockwood , David E. Taylor , David Parlour Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Jinghuan Chen , Jaekyun Moon , Kia Bazargan A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Wei-Cheng Lai , Kwang-Ting Cheng , Li Chen , Sujit Dey Embedded software-based self-testing for SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Kaushik Roy , Jaume Segura A novel wavelet transform based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Attarha , Mehrdad Nourani Signal integrity fault analysis using reduced-order modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jia Liou , Li-C. Wang , Kwang-Ting Cheng , Jennifer Dworak , M. Ray Mercer , Rohit Kapur , Thomas W. Williams Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Berthet Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry. [Citation Graph (0, 0)][DBLP ] Conf ] Yahong Cao , Yu-Min Lee , Tsung-Hao Chen , Charlie Chung-Ping Chen HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Bodapati , Farid N. Najm High-level current macro-model for power-grid analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Brian W. Amick , Claude R. Gauthier , Dean Liu Macro-modeling concepts for the chip electrical interface. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Zheng , Lawrence T. Pileggi Modeling and analysis of regular symmetrically structured power/ground distribution networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mustafa Badaroglu , Kris Tiri , Stéphane Donnay , Piet Wambacq , Hugo De Man , Ingrid Verbauwhede , Georges G. E. Gielen Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP ] Conf ] Tiberiu Chelcea , Steven M. Nowick Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Kondratyev , Kelvin Lwin Design of asynchronous circuits by synchronous CAD tools. [Citation Graph (0, 0)][DBLP ] Conf ] Christos P. Sotiriou Implementing asynchronous circuits using a conventional EDA tool-flow. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Iwama , Yahiko Kambayashi , Shigeru Yamashita Transformation rules for designing CNOT-based quantum circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Bernasconi , Valentina Ciriani , Fabrizio Luccio , Linda Pagli Fast three-level logic minimization based on autosymmetry. [Citation Graph (0, 0)][DBLP ] Conf ] Walter Daems , Georges G. E. Gielen , Willy M. C. Sansen An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hongzhou Liu , Amith Singhee , Rob A. Rutenbar , L. Richard Carley Remembrance of circuits past: macromodeling by data mining in large analog design spaces. [Citation Graph (0, 0)][DBLP ] Conf ] Ovidiu Bajdechi , Johan H. Huijsing , Georges G. E. Gielen Optimal design of delta-sigma ADCs by design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Vandenbussche , K. Uyttenhove , Erik Lauwers , Michiel Steyaert , Georges G. E. Gielen Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Murugavel , N. Ranganathan Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Pawan Kapur , Gaurav Chandra , Krishna Saraswat Power estimation in global interconnects and its reduction using a novel repeater optimization methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Seong-Ook Jung , Ki-Wook Kim , Sung-Mo Kang Low-swing clock domino logic incorporating dual supply and dual threshold voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Agarwal , Hai Li , Kaushik Roy DRG-cache: a data retention gated-ground cache for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Gary Smith , Daya Nadamuni , Sharad Malik , Rick Chapman , John Fogelin , Kurt Keutzer , Grant Martin , Brian Bailey Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? [Citation Graph (0, 0)][DBLP ] Conf ] Mohab Anis , Mohamed Mahmoud , Mohamed I. Elmasry , Shawki Areibi Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. [Citation Graph (0, 0)][DBLP ] Conf ] Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven M. Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-In Kang , Jinwoo Suh , Stephen P. Crago An optimal voltage synthesis technique for a power-efficient satellite application. [Citation Graph (0, 0)][DBLP ] Conf ] Michael H. Perrott Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Baolin Yang , Joel R. Phillips Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury A time-domain RF steady-state method for closely spaced tones. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgio Casinovi An algorithm for frequency-domain noise analysis in nonlinear systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chantal Ykman-Couvreur , J. Lambrecht , Diederik Verkest , Francky Catthoor , Aristides Nikologiannis , George E. Konstantoulakis System-level performance optimization of the data queueing memory management in high-speed network processors. [Citation Graph (0, 0)][DBLP ] Conf ] Terry Tao Ye , Giovanni De Micheli , Luca Benini Analysis of power consumption on switch fabrics in network routers. [Citation Graph (0, 0)][DBLP ] Conf ] David Whelihan , Herman Schmit Memory optimization in single chip network switch fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Piet Vanassche , Georges G. E. Gielen , Willy M. C. Sansen Behavioral modeling of (coupled) harmonic oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Walter Hartong , Lars Hedrich , Erich Barke Model checking algorithms for analog verification. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Mades , Manfred Glesner Regularization of hierarchical VHDL-AMS models using bipartite graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Yehia Massoud , Jacob White Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Orshansky , Kurt Keutzer A general probabilistic framework for worst case timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Zeng , Magdy S. Abadir , Jacob A. Abraham False timing path identification using ATPG techniques and delay-based information. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jia Liou , Angela Krstic , Li-C. Wang , Kwang-Ting Cheng False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. [Citation Graph (0, 0)][DBLP ] Conf ] Srihari Cadambi , Chandra Mulpuri , Pranav Ashar A fast, inexpensive and scalable hardware acceleration technique for functional simulation. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Dill , Nate James , Shishpal Rawat , Gérard Berry , Limor Fix , Harry Foster , Rajeev K. Ranjan , Gunnar Stålmarck , Curt Widdoes Formal verification methods: getting around the brick wall. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Hrkic , John Lillis S-Tree: a technique for buffered routing tree synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , D. F. Wong , Xiaoping Tang An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , William Nicholls An efficient routing database. [Citation Graph (0, 0)][DBLP ] Conf ] Ferid Gharsalli , Samy Meftali , Frédéric Rousseau , Ahmed Amine Jerraya Automatic generation of embedded memory wrapper for multiprocessor SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Siegmund , Dietmar Müller A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Seo , Taewhan Kim , Preeti Ranjan Panda An integrated algorithm for memory allocation and assignment in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] María C. Molina , José M. Mendías , Román Hermida High-level synthesis of multiple-precision circuitsindependent of data-objects length. [Citation Graph (0, 0)][DBLP ] Conf ] Samarjit Chakraborty , Thomas Erlebach , Simon Künzli , Lothar Thiele Schedulability of event-driven code blocks in real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Wolf , Jan Staschulat , Rolf Ernst Associative caches in formal software timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Alok N. Choudhary Compiler-directed scratch pad memory hierarchy design and management. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Schaumont , Henry Kuo , Ingrid Verbauwhede Unlocking the design secrets of a 2.29 Gb/s Rijndael processor. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Richardson , Lun Bin Huang , Razak Hossain , Tommy Zounes , Naresh Soni , Julian Lewis The iCOREtm 520 MHz synthesizable CPU core. [Citation Graph (0, 0)][DBLP ] Conf ] Gokhan Memik , William H. Mangione-Smith A flexible accelerator for layer 7 networking applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey , Joachim Kunkel , Dennis Brophy , Raul Camposano , Davoud Samani , Larry Lerner , Rick Hetherington What's the next EDA driver? [Citation Graph (0, 0)][DBLP ] Conf ] Sarma B. K. Vrudhula , David Blaauw , Supamas Sirichotiyakul Estimation of the likelihood of capacitive coupling noise. [Citation Graph (0, 0)][DBLP ] Conf ] Paul B. Morton , Wayne Wei-Ming Dai Crosstalk noise estimation for noise management. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Krauter , David Widiger Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Z. Ma , Lei He Towards global routing with RLC crosstalk constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Anshuman Chandra , Krishnendu Chakrabarty Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas Kay , Sung Chung , Samiha Mourad Embedded test control schemes for compression in SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Krishnendu Chakrabarty , Erik Jan Marinissen Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Kanishka Lahiri , Sujit Dey , Anand Raghunathan Communication architecture based power management for battery efficient system design. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Delaluz , Anand Sivasubramaniam , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin Scheduler-based DRAM energy management. [Citation Graph (0, 0)][DBLP ] Conf ] Ismail Kadayif , Mahmut T. Kandemir , Ugur Sezer An integer linear programming based approach for parallelizing applications in On-chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian Embedding infrastructure IP for SOC yield improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Charles E. Stroud , Marty Emmert Using embedded FPGAs for SoC yield improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Gunnar Andersson , Per Bjesse , Byron Cook , Ziyad Hanna A proof engine approach to solving combinational design automation problems. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Arathi Ramani , Igor L. Markov , Karem A. Sakallah Solving difficult SAT instances in the presence of symmetry. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Brian D. Sierawski , Karem A. Sakallah Satometer: how much have we searched? [Citation Graph (0, 0)][DBLP ] Conf ] Slawomir Pilarski , Gracia Hu SAT with partial clauses and back-leaps. [Citation Graph (0, 0)][DBLP ] Conf ] Malay K. Ganai , Pranav Ashar , Aarti Gupta , Lintao Zhang , Sharad Malik Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. [Citation Graph (0, 0)][DBLP ] Conf ] Hemant Mahawar , Vivek Sarin , Weiping Shi A solenoidal basis method for efficient inductance extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Lin , Michael W. Beattie , Lawrence T. Pileggi On the efficacy of simplified 2D on-chip inductance models. [Citation Graph (0, 0)][DBLP ] Conf ] Raguraman Venkatesan , Jeffrey A. Davis , James D. Meindl A physical model for the transient response of capacitively loaded distributed rlc interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Adil Koukab , Catherine Dehollain , Michel J. Declercq HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Eelco Schrik , N. P. van der Meijs Combined BEM/FEM substrate resistance modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Anand Raghunathan , Nachiketh R. Potlapally , Murugan Sankaradass System design methodologies for a wireless security processing platform. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Pinto , Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli Constraint-driven communication synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Wander O. Cesário , Amer Baghdadi , Lovic Gauthier , Damien Lyonnard , Gabriela Nicolescu , Yanick Paviot , Sungjoo Yoo , Ahmed Amine Jerraya , Mario Diaz-Nava Component-based design approach for multicore SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Varatkar , Radu Marculescu Traffic analysis for on-chip networks design of multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kanna Shimizu , David L. Dill Deriving a simulation input generator and a coverage metric from a formal specification. [Citation Graph (0, 0)][DBLP ] Conf ] Oded Lachish , Eitan Marcus , Shmuel Ur , Avi Ziv Hole analysis for functional coverage data. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Sheng , Koichiro Takayama , Michael S. Hsiao Effective safety property checking using simulation-based sequential ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Bartley , Darren Galpin , Tim Blackmore A comparison of three verification techniques: directed testing, pseudo-random testing and property checking. [Citation Graph (0, 0)][DBLP ] Conf ] Carla-Fabiana Chiasserini , Pavan Nuggehalli , Vikram Srinivasan Energy-efficient communication protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh R. Shanbhag Reliable and energy-efficient digital signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Michiel Steyaert , Peter J. Vancorenland CMOS: a paradigm for low power wireless? [Citation Graph (0, 0)][DBLP ] Conf ] Jai-Ming Lin , Yao-Wen Chang TCG-S: orthogonal coupling of P* -admissible representations for general floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoping Tang , D. F. Wong Floorplanning with alignment and performance constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ke Zhong , Shantanu Dutt Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. [Citation Graph (0, 0)][DBLP ] Conf ] Lauren Hui Chen , Malgorzata Marek-Sadowska , Forrest Brewer Coping with buffer delay change due to power and ground noise. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard N. Sheehan Osculating Thevenin model for predicting delay and slew of capacitively characterized cells. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Hoon Choi , Kaushik Roy , Florentin Dartu Timed pattern generation for noise-on-delay calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Jaesik Lee , Ki-Wook Kim , Sung-Mo Kang VeriCDF: a new verification methodology for charged device failures. [Citation Graph (0, 0)][DBLP ] Conf ] Lothar Thiele , Samarjit Chakraborty , Matthias Gries , Simon Künzli A framework for evaluating design tradeoffs in packet processing architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Bona , Mariagiovanna Sami , Donatella Sciuto , Vittorio Zaccaria , Cristina Silvano , Roberto Zafalon Energy estimation and optimization of embedded VLIW processors based on instruction clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Yongsoo Joo , Yongseok Choi , Hojun Shim , Hyung Gyu Lee , Kwanho Kim , Naehyuck Chang Energy exploration and reduction of SDRAM memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Gupta , Nick Savoiu , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau , Timothy Kam , Michael Kishinevsky , Shai Rotem Coordinated transformations for high-level synthesis of high performance microprocessor blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer L. Wong , Seapahn Megerian , Miodrag Potkonjak Forward-looking objective functions: concept & applications in high level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Farinaz Koushanfar , Jennifer L. Wong , Jessica Feng , Miodrag Potkonjak ILP-based engineering change. [Citation Graph (0, 0)][DBLP ] Conf ] 