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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2002 (conf/dac/2002)

  1. Moshe Gavrielov, Richard Goering, Lucio Lanza, Vishal Saluja, Jay Vleeschhouwer
    Wall street evaluates EDA. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:1- [Conf]
  2. Michael J. Wirthlin, Brian McMurtrey
    IP delivery for FPGAs using Applets and JHDL. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:2-7 [Conf]
  3. Seapahn Megerian, Milenko Drinic, Miodrag Potkonjak
    Watermarking integer linear programming solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:8-13 [Conf]
  4. Fabrice Bernardi, Jean François Santucci
    Model design using hierarchical web-based libraries. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:14-17 [Conf]
  5. Milenko Drinic, Darko Kirovski
    Behavioral synthesis via engineering change. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:18-21 [Conf]
  6. Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
    A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:22-27 [Conf]
  7. Roman L. Lysecky, Susan Cotterell, Frank Vahid
    A fast on-chip profiler memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:28-33 [Conf]
  8. Haris Lekatsas, Jörg Henkel, Venkata Jakkula
    Design of an one-cycle decompression hardware for performance increase in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:34-39 [Conf]
  9. Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
    A factorization-based framework for passivity-preserving model reduction of RLC systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:40-45 [Conf]
  10. Luca Daniel, Joel R. Phillips
    Model order reduction for strictly passive and causal distributed systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:46-51 [Conf]
  11. Joel R. Phillips, Luca Daniel, Luis Miguel Silveira
    Guaranteed passive balancing transformations for model order reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:52-57 [Conf]
  12. Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski
    Uncertainty-aware circuit optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:58-63 [Conf]
  13. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    Congestion-driven codesign of power and signal networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:64-69 [Conf]
  14. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    On metrics for comparing routability estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:70-75 [Conf]
  15. Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven
    Tools or users: which is the bigger bottleneck? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:76-77 [Conf]
  16. George Sery, Shekhar Borkar, Vivek De
    Life is CMOS: why chase the life after? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:78-83 [Conf]
  17. H. Bernhard Pogge
    The next chip challenge: effective methods for viable mixed technology SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:84-87 [Conf]
  18. Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
    Few electron devices: towards hybrid CMOS-SET integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:88-93 [Conf]
  19. R. Martel, V. Derycke, J. Appenzeller, S. Wind, Ph. Avouris
    Carbon nanotube field-effect transistors and logic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:94-98 [Conf]
  20. Valeria Bertacco, Kunle Olukotun
    Efficient state representation for symbolic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:99-104 [Conf]
  21. Alfred Kölbl, James H. Kukula, Kurt Antreich, Robert F. Damiano
    Handling special constructs in symbolic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:105-110 [Conf]
  22. Scott Hazelhurst, Osnat Weissberg, Gila Kamhi, Limor Fix
    A hybrid verification approach: getting deep into the design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:111-116 [Conf]
  23. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Can BDDs compete with SAT solvers on bounded model checking? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:117-122 [Conf]
  24. Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
    RTL c-based methodology for designing and verifying a multi-threaded processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:123-128 [Conf]
  25. Marcio T. Oliveira, Alan J. Hu
    High-Level specification and automatic generation of IP interface monitors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:129-134 [Conf]
  26. Kerstin Eder, Geoff Barrett
    Achieving maximum performance: a method for the verification of interlocked pipeline control logic. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:135-140 [Conf]
  27. Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee
    Formal verification of module interfaces against real time specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:141-145 [Conf]
  28. Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu
    Automated timing model generation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:146-151 [Conf]
  29. Cho W. Moon, Harish Kriplani, Krishna P. Belkhale
    Timing model extraction of hierarchical blocks by graph reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:152-157 [Conf]
  30. Martin Foltin, Brian Foutz, Sean Tyler
    Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:158-163 [Conf]
  31. Hiroyuki Higuchi
    An implication-based method to detect multi-cycle paths in large sequential circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:164-169 [Conf]
  32. Sungmee Park, Kenneth Mackenzie, Sundaresan Jayaraman
    The wearable motherboard: a framework for personalized mobile information processing (PMIP). [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:170-174 [Conf]
  33. Diana Marculescu, Radu Marculescu, Pradeep K. Khosla
    Challenges and opportunities in electronic textiles modeling and optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:175-180 [Conf]
  34. Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore
    Analog intellectual property: now? Or never? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:181-182 [Conf]
  35. Yumin Zhang, Xiaobo Hu, Danny Z. Chen
    Task scheduling and voltage selection for energy minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:183-188 [Conf]
  36. Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti
    Battery-conscious task sequencing for portable devices including voltage/clock scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:189-194 [Conf]
  37. Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karaköy
    An energy saving strategy based on adaptive loop parallelization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:195-200 [Conf]
  38. Fan Mo, Robert K. Brayton
    River PLAs: a regular circuit structure. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:201-206 [Conf]
  39. Junhyung Um, Taewhan Kim
    Layout-aware synthesis of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:207-212 [Conf]
  40. Victor De La Luz, Mahmut T. Kandemir, Ibrahim Kolcu
    Automatic data migration for reducing energy consumption in multi-bank memory systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:213-218 [Conf]
  41. Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary
    Exploiting shared scratch pad memory space in embedded multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:219-224 [Conf]
  42. Yoonseo Choi, Taewhan Kim
    Address assignment combined with scheduling in DSP code generation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:225-230 [Conf]
  43. Edward H. Sargent
    Multifunctional photonic integration for the agile optical internet. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:231-234 [Conf]
  44. James G. Maloney, Brian E. Brewington, Curtis R. Menyuk
    Computer aided design of long-haul optical transmission systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:235- [Conf]
  45. Timothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Mark Kahrs, Donald M. Chiarulli
    A fast optical propagation technique for modeling micro-optical systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:236-241 [Conf]
  46. Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi
    Nanometer design: what hurts next...? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:242- [Conf]
  47. Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
    Low-cost sequential ATPG with clock-control DFT. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:243-248 [Conf]
  48. Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston
    Effective diagnostics through interval unloads in a BIST environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:249-254 [Conf]
  49. Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
    On output response compression in the presence of unknown output values. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:255-258 [Conf]
  50. Li Chen, Sujit Dey
    Software-based diagnosis for processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:259-262 [Conf]
  51. Xun Liu, Marios C. Papaefthymiou
    Design of a high-throughput low-power IS95 Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:263-268 [Conf]
  52. Daniel Ragan, Peter Sandborn, Paul Stoaks
    A detailed cost model for concurrent use with hardware/software co-design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:269-274 [Conf]
  53. Hyunok Oh, Soonhoi Ha
    Efficient code synthesis from extended dataflow graphs for multimedia applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:275-280 [Conf]
  54. Ingo Sander, Axel Jantsch
    Transformation based communication and clock domain refinement for system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:281-286 [Conf]
  55. Kai Richter, Dirk Ziegenbein, Marek Jersak, Rolf Ernst
    Model composition for scheduling analysis in platform design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:287-292 [Conf]
  56. Jong-Yeol Lee, In-Cheol Park
    Timed compiled-code simulation of embedded software for performance analysis of SOC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:293-298 [Conf]
  57. Simon Jolly, Atanas N. Parashkevov, Tim McDougall
    Automated equivalence checking of switch level circuits . [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:299-304 [Conf]
  58. Demos Anastasakis, Robert F. Damiano, Hi-Keung Tony Ma, Ted Stanion
    A practical and efficient method for compare-point matching. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:305-310 [Conf]
  59. Ying-Tsai Chang, Kwang-Ting Cheng
    Self-referential verification of gate-level implementations of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:311-316 [Conf]
  60. Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada
    Whither (or wither?) ASIC handoff? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:317-318 [Conf]
  61. Yunjian Jiang, Robert K. Brayton
    Software synthesis from synchronous specifications using logic simulation techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:319-324 [Conf]
  62. Armita Peymandoust, Giovanni De Micheli, Tajana Simunic
    Complex library mapping for embedded software using symbolic algebra. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:325-330 [Conf]
  63. Maghsoud Abbaspour, Jianwen Zhu
    Retargetable binary utilities. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:331-336 [Conf]
  64. Zhining Huang, Sharad Malik
    Exploiting operation level parallelism through dynamically reconfigurable datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:337-342 [Conf]
  65. Edson L. Horta, John W. Lockwood, David E. Taylor, David Parlour
    Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:343-348 [Conf]
  66. Jinghuan Chen, Jaekyun Moon, Kia Bazargan
    A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:349-354 [Conf]
  67. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded software-based self-testing for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:355-360 [Conf]
  68. Swarup Bhunia, Kaushik Roy, Jaume Segura
    A novel wavelet transform based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:361-366 [Conf]
  69. Amir Attarha, Mehrdad Nourani
    Signal integrity fault analysis using reduced-order modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:367-370 [Conf]
  70. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  71. Christian Berthet
    Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:375-378 [Conf]
  72. Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen
    HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:379-384 [Conf]
  73. Srinivas Bodapati, Farid N. Najm
    High-level current macro-model for power-grid analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:385-390 [Conf]
  74. Brian W. Amick, Claude R. Gauthier, Dean Liu
    Macro-modeling concepts for the chip electrical interface. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:391-394 [Conf]
  75. Hui Zheng, Lawrence T. Pileggi
    Modeling and analysis of regular symmetrically structured power/ground distribution networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:395-398 [Conf]
  76. Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
    Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:399-404 [Conf]
  77. Tiberiu Chelcea, Steven M. Nowick
    Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:405-410 [Conf]
  78. Alex Kondratyev, Kelvin Lwin
    Design of asynchronous circuits by synchronous CAD tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:411-414 [Conf]
  79. Christos P. Sotiriou
    Implementing asynchronous circuits using a conventional EDA tool-flow. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:415-418 [Conf]
  80. Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita
    Transformation rules for designing CNOT-based quantum circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:419-424 [Conf]
  81. Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
    Fast three-level logic minimization based on autosymmetry. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:425-430 [Conf]
  82. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:431-436 [Conf]
  83. Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley
    Remembrance of circuits past: macromodeling by data mining in large analog design spaces. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:437-442 [Conf]
  84. Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen
    Optimal design of delta-sigma ADCs by design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:443-448 [Conf]
  85. Jan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen
    Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:449-454 [Conf]
  86. Ashok K. Murugavel, N. Ranganathan
    Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:455-460 [Conf]
  87. Pawan Kapur, Gaurav Chandra, Krishna Saraswat
    Power estimation in global interconnects and its reduction using a novel repeater optimization methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:461-466 [Conf]
  88. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Low-swing clock domino logic incorporating dual supply and dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:467-472 [Conf]
  89. Amit Agarwal, Hai Li, Kaushik Roy
    DRG-cache: a data retention gated-ground cache for low power. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:473-478 [Conf]
  90. Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey
    Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:479- [Conf]
  91. Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi
    Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:480-485 [Conf]
  92. Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
    Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:486-491 [Conf]
  93. Dong-In Kang, Jinwoo Suh, Stephen P. Crago
    An optimal voltage synthesis technique for a power-efficient satellite application. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:492-497 [Conf]
  94. Michael H. Perrott
    Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:498-503 [Conf]
  95. Baolin Yang, Joel R. Phillips
    Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:504-509 [Conf]
  96. Jaijeet S. Roychowdhury
    A time-domain RF steady-state method for closely spaced tones. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:510-513 [Conf]
  97. Giorgio Casinovi
    An algorithm for frequency-domain noise analysis in nonlinear systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:514-517 [Conf]
  98. Chantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Aristides Nikologiannis, George E. Konstantoulakis
    System-level performance optimization of the data queueing memory management in high-speed network processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:518-523 [Conf]
  99. Terry Tao Ye, Giovanni De Micheli, Luca Benini
    Analysis of power consumption on switch fabrics in network routers. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:524-529 [Conf]
  100. David Whelihan, Herman Schmit
    Memory optimization in single chip network switch fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:530-535 [Conf]
  101. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Behavioral modeling of (coupled) harmonic oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:536-541 [Conf]
  102. Walter Hartong, Lars Hedrich, Erich Barke
    Model checking algorithms for analog verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:542-547 [Conf]
  103. Jochen Mades, Manfred Glesner
    Regularization of hierarchical VHDL-AMS models using bipartite graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:548-551 [Conf]
  104. Yehia Massoud, Jacob White
    Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:552-555 [Conf]
  105. Michael Orshansky, Kurt Keutzer
    A general probabilistic framework for worst case timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:556-561 [Conf]
  106. Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
    False timing path identification using ATPG techniques and delay-based information. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:562-565 [Conf]
  107. Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:566-569 [Conf]
  108. Srihari Cadambi, Chandra Mulpuri, Pranav Ashar
    A fast, inexpensive and scalable hardware acceleration technique for functional simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:570-575 [Conf]
  109. David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes
    Formal verification methods: getting around the brick wall. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:576-577 [Conf]
  110. Milos Hrkic, John Lillis
    S-Tree: a technique for buffered routing tree synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:578-583 [Conf]
  111. Hua Xiang, D. F. Wong, Xiaoping Tang
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:584-589 [Conf]
  112. Narendra V. Shenoy, William Nicholls
    An efficient routing database. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:590-595 [Conf]
  113. Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic generation of embedded memory wrapper for multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:596-601 [Conf]
  114. Robert Siegmund, Dietmar Müller
    A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:602-607 [Conf]
  115. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    An integrated algorithm for memory allocation and assignment in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:608-611 [Conf]
  116. María C. Molina, José M. Mendías, Román Hermida
    High-level synthesis of multiple-precision circuitsindependent of data-objects length. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:612-615 [Conf]
  117. Samarjit Chakraborty, Thomas Erlebach, Simon Künzli, Lothar Thiele
    Schedulability of event-driven code blocks in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:616-621 [Conf]
  118. Fabian Wolf, Jan Staschulat, Rolf Ernst
    Associative caches in formal software timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:622-627 [Conf]
  119. Mahmut T. Kandemir, Alok N. Choudhary
    Compiler-directed scratch pad memory hierarchy design and management. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:628-633 [Conf]
  120. Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
    Unlocking the design secrets of a 2.29 Gb/s Rijndael processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:634-639 [Conf]
  121. Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis
    The iCOREtm 520 MHz synthesizable CPU core. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:640-645 [Conf]
  122. Gokhan Memik, William H. Mangione-Smith
    A flexible accelerator for layer 7 networking applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:646-651 [Conf]
  123. Jan M. Rabaey, Joachim Kunkel, Dennis Brophy, Raul Camposano, Davoud Samani, Larry Lerner, Rick Hetherington
    What's the next EDA driver? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:652- [Conf]
  124. Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul
    Estimation of the likelihood of capacitive coupling noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:653-658 [Conf]
  125. Paul B. Morton, Wayne Wei-Ming Dai
    Crosstalk noise estimation for noise management. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:659-664 [Conf]
  126. Byron Krauter, David Widiger
    Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:665-668 [Conf]
  127. James D. Z. Ma, Lei He
    Towards global routing with RLC crosstalk constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:669-672 [Conf]
  128. Anshuman Chandra, Krishnendu Chakrabarty
    Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:673-678 [Conf]
  129. Douglas Kay, Sung Chung, Samiha Mourad
    Embedded test control schemes for compression in SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:679-684 [Conf]
  130. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:685-690 [Conf]
  131. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication architecture based power management for battery efficient system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:691-696 [Conf]
  132. Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Scheduler-based DRAM energy management. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:697-702 [Conf]
  133. Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
    An integer linear programming based approach for parallelizing applications in On-chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:703-708 [Conf]
  134. Yervant Zorian
    Embedding infrastructure IP for SOC yield improvement. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:709-712 [Conf]
  135. Miron Abramovici, Charles E. Stroud, Marty Emmert
    Using embedded FPGAs for SoC yield improvement. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:713-724 [Conf]
  136. Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
    A proof engine approach to solving combinational design automation problems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:725-730 [Conf]
  137. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Solving difficult SAT instances in the presence of symmetry. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:731-736 [Conf]
  138. Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah
    Satometer: how much have we searched? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:737-742 [Conf]
  139. Slawomir Pilarski, Gracia Hu
    SAT with partial clauses and back-leaps. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:743-746 [Conf]
  140. Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik
    Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:747-750 [Conf]
  141. Hemant Mahawar, Vivek Sarin, Weiping Shi
    A solenoidal basis method for efficient inductance extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:751-756 [Conf]
  142. Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
    On the efficacy of simplified 2D on-chip inductance models. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:757-762 [Conf]
  143. Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl
    A physical model for the transient response of capacitively loaded distributed rlc interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:763-766 [Conf]
  144. Adil Koukab, Catherine Dehollain, Michel J. Declercq
    HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:767-770 [Conf]
  145. Eelco Schrik, N. P. van der Meijs
    Combined BEM/FEM substrate resistance modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:771-776 [Conf]
  146. Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
    System design methodologies for a wireless security processing platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:777-782 [Conf]
  147. Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Constraint-driven communication synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:783-788 [Conf]
  148. Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava
    Component-based design approach for multicore SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:789-794 [Conf]
  149. Girish Varatkar, Radu Marculescu
    Traffic analysis for on-chip networks design of multimedia applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:795-800 [Conf]
  150. Kanna Shimizu, David L. Dill
    Deriving a simulation input generator and a coverage metric from a formal specification. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:801-806 [Conf]
  151. Oded Lachish, Eitan Marcus, Shmuel Ur, Avi Ziv
    Hole analysis for functional coverage data. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:807-812 [Conf]
  152. Shuo Sheng, Koichiro Takayama, Michael S. Hsiao
    Effective safety property checking using simulation-based sequential ATPG. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:813-818 [Conf]
  153. Mike Bartley, Darren Galpin, Tim Blackmore
    A comparison of three verification techniques: directed testing, pseudo-random testing and property checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:819-823 [Conf]
  154. Carla-Fabiana Chiasserini, Pavan Nuggehalli, Vikram Srinivasan
    Energy-efficient communication protocols. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:824-829 [Conf]
  155. Naresh R. Shanbhag
    Reliable and energy-efficient digital signal processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:830-835 [Conf]
  156. Michiel Steyaert, Peter J. Vancorenland
    CMOS: a paradigm for low power wireless? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:836-841 [Conf]
  157. Jai-Ming Lin, Yao-Wen Chang
    TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:842-847 [Conf]
  158. Xiaoping Tang, D. F. Wong
    Floorplanning with alignment and performance constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:848-853 [Conf]
  159. Ke Zhong, Shantanu Dutt
    Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:854-859 [Conf]
  160. Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
    Coping with buffer delay change due to power and ground noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:860-865 [Conf]
  161. Bernard N. Sheehan
    Osculating Thevenin model for predicting delay and slew of capacitively characterized cells. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:866-869 [Conf]
  162. Seung Hoon Choi, Kaushik Roy, Florentin Dartu
    Timed pattern generation for noise-on-delay calculation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:870-873 [Conf]
  163. Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang
    VeriCDF: a new verification methodology for charged device failures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:874-879 [Conf]
  164. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli
    A framework for evaluating design tradeoffs in packet processing architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:880-885 [Conf]
  165. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    Energy estimation and optimization of embedded VLIW processors based on instruction clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:886-891 [Conf]
  166. Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu Lee, Kwanho Kim, Naehyuck Chang
    Energy exploration and reduction of SDRAM memory systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:892-897 [Conf]
  167. Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem
    Coordinated transformations for high-level synthesis of high performance microprocessor blocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:898-903 [Conf]
  168. Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak
    Forward-looking objective functions: concept & applications in high level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:904-909 [Conf]
  169. Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng, Miodrag Potkonjak
    ILP-based engineering change. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:910-915 [Conf]
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