The SCEAS System
Navigation Menu

Conferences in DBLP

Design Automation Conference (DAC) (dac)
2006 (conf/dac/2006)

  1. Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu
    How will the fabless model survive? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1-2 [Conf]
  2. Doug Josephson
    The good, the bad, and the ugly of silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:3-6 [Conf]
  3. Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller
    A reconfigurable design-for-debug infrastructure for SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:7-12 [Conf]
  4. Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang
    Visibility enhancement for silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:13-18 [Conf]
  5. Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
    A CPPLL hierarchical optimization methodology considering jitter, power and locking time. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:19-24 [Conf]
  6. Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
    Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:25-30 [Conf]
  7. Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
    Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:31-36 [Conf]
  8. Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino
    A real time budgeting method for module-level-pipelined bus based system using bus scenarios. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:37-42 [Conf]
  9. Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
    Exploiting forwarding to improve data bandwidth of instruction-set extensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:43-48 [Conf]
  10. Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt
    Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:49-52 [Conf]
  11. Xinping Zhu, Wei Qin
    Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:53-56 [Conf]
  12. Kanak Agarwal, Sani R. Nassif
    Statistical analysis of SRAM cell stability. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:57-62 [Conf]
  13. Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
    Criticality computation in parameterized statistical timing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:63-68 [Conf]
  14. Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
    Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:69-72 [Conf]
  15. Jie Yang, Ethan Cohen, Cyrus Tabery, Norma Rodriguez, Mark Craig
    An up-stream design auto-fix flow for manufacturability enhancement. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:73-76 [Conf]
  16. G. Singer, Philippe Magarshack, Dennis Buss, F.-C. Hsu, H.-K. Kang
    "The IC nanometer race -- what will it take to win?". [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:77-78 [Conf]
  17. David Brier, Raj S. Mitra
    Use of C/C++ models for architecture exploration and verification of DSPs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:79-84 [Conf]
  18. Alistair Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard
    Maintaining consistency between systemC and RTL system designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:85-89 [Conf]
  19. Stuart Swan
    SystemC transaction level models and RTL verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:90-92 [Conf]
  20. Philippe Georgelin, Venkat Krishnaswamy
    Towards a C++-based design methodology facilitating sequential equivalence checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:93-96 [Conf]
  21. Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
    Charge recycling in MTCMOS circuits: concept and analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:97-102 [Conf]
  22. Xin Li, Jiayong Le, Lawrence T. Pileggi
    Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:103-108 [Conf]
  23. Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo
    Physical design methodology of power gating circuits for standard-cell-based design. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:109-112 [Conf]
  24. Kaijian Shi, David Howard
    Challenges in sleep transistor design and implementation in low-power designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:113-116 [Conf]
  25. Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
    A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:117-120 [Conf]
  26. De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh
    Timing driven power gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:121-124 [Conf]
  27. Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev
    A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:125-130 [Conf]
  28. Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
    An automated, reconfigurable, low-power RFID tag. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:131-136 [Conf]
  29. Hyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang
    Design space exploration and prototyping for on-chip multimedia applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:137-142 [Conf]
  30. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
    Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:143-148 [Conf]
  31. Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
    Refined statistical static timing analysis through. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:149-154 [Conf]
  32. Jaskirat Singh, Sachin S. Sapatnekar
    Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:155-160 [Conf]
  33. Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky
    Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:161-166 [Conf]
  34. Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
    Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:167-172 [Conf]
  35. Ron Wilson, Yervant Zorian
    Decision-making for complex SoCs in consumer electronic products. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:173- [Conf]
  36. A. Yang, R. Chandra, S. Burke, J. A. DeLaCruz, S. Santhanam, U. Ko
    Entering the hot zone: can you handle the heat and be cool? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:174-175 [Conf]
  37. J. W. McPherson
    Reliability challenges for 45nm and beyond. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:176-181 [Conf]
  38. Zhihong Liu, Bruce McGaughy, James Z. Ma
    Design tools for reliability analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:182-187 [Conf]
  39. Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar
    Design in reliability for communication designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:188-192 [Conf]
  40. T. Pompl, C. Schlünder, M. Hommel, H. Nielen, J. Schneider
    Practical aspects of reliability analysis for IC designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:193-198 [Conf]
  41. Sanjay Pant, Eli Chiprout
    Power grid physics and implications for CAD. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:199-204 [Conf]
  42. Hao Yu, Yiyu Shi, Lei He
    Fast analysis of structured power grid by triangularization based structure preserving model order reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:205-210 [Conf]
  43. Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
    Stochastic variational analysis of large power grids considering intra-die correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:211-216 [Conf]
  44. Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
    A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:217-222 [Conf]
  45. Ziv Nevo, Monica Farkash
    Distributed dynamic BDD reordering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:223-228 [Conf]
  46. Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli
    SAT sweeping with local observability don't-cares. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:229-234 [Conf]
  47. Chao Wang, Aarti Gupta, Malay K. Ganai
    Predicate learning and selective theory deduction for a difference logic solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:235-240 [Conf]
  48. Vishnu C. Vimjam, Michael S. Hsiao
    Fast illegal state identification for improving SAT-based induction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:241-246 [Conf]
  49. Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout
    A multi-port current source model for multiple-input switching effects in CMOS library cells. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:247-252 [Conf]
  50. Hanif Fatemi, Shahin Nazarian, Massoud Pedram
    Statistical logic cell delay analysis using a current-based model. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:253-256 [Conf]
  51. N. Wong, V. Balakrishnan
    Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:257-260 [Conf]
  52. N. Wong, C. K. Chu
    A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:261-266 [Conf]
  53. Peng Li, Weiping Shi
    Model order reduction of linear networks with massive ports via frequency-dependent port packing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:267-272 [Conf]
  54. Nic Mokhoff, Yervant Zorian
    Tradeoffs and choices for emerging SoCs in high-end applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:273- [Conf]
  55. Grant Martin
    Overview of the MPSoC design challenge. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:274-279 [Conf]
  56. Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot
    Programming models and HW-SW interfaces abstraction for multi-processor SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:280-285 [Conf]
  57. Peter Flake, Simon J. Davidmann, Frank Schirrmeister
    System-level exploration tools for MPSoC designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:286-287 [Conf]
  58. Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
    Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:288-289 [Conf]
  59. Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho
    A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:290-291 [Conf]
  60. Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno
    Hierarchical power distribution and power management scheme for a single chip mobile processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:292-295 [Conf]
  61. Mandar Waghmode, Zhuo Li, Weiping Shi
    Buffer insertion in large circuits with constructive solution search techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:296-301 [Conf]
  62. Yuantao Peng, Xun Liu
    Low-power repeater insertion with both delay and slew rate constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:302-307 [Conf]
  63. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
    Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:308-313 [Conf]
  64. Vikram Iyengar, Gary Grise, Mark Taylor
    A flexible and scalable methodology for GHz-speed structural test. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:314-319 [Conf]
  65. Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
    Timing-based delay test for screening small delay defects. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:320-325 [Conf]
  66. Amitava Majumdar, Wei-Yu Chen, Jun Guo
    Hold time validation on silicon and the relevance of hazards in timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:326-331 [Conf]
  67. Alon Gluska
    Practical methods in coverage-oriented verification of the merom microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:332-337 [Conf]
  68. Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson
    Verification of the cell broadband engineTM processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:338-343 [Conf]
  69. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    Shielding against design flaws with field repairable control logic. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:344-347 [Conf]
  70. Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen
    Scheduling-based test-case generation for verification of multimedia SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:348-351 [Conf]
  71. Xiangrong Zhou, Peter Petrov
    Rapid and low-cost context-switch through embedded processor customization for real-time and control applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:352-357 [Conf]
  72. Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
    Efficient detection and exploitation of infeasible paths for software timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:358-363 [Conf]
  73. Po-Kuan Huang, Soheil Ghiasi
    Leakage-aware intraprogram voltage scaling for embedded processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:364-369 [Conf]
  74. Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch
    Building a standard ESL design and verification methodology: is it just a dream? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:370-371 [Conf]
  75. Andrew B. Kahng
    CAD challenges for leading-edge multimedia designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:372- [Conf]
  76. Minsik Cho, David Z. Pan
    BoxRouter: a new global router based on box expansion and progressive ILP. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:373-378 [Conf]
  77. Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
    Steiner network construction for timing critical nets. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:379-384 [Conf]
  78. Yiyu Shi, Paul Mesa, Hao Yu, Lei He
    Circuit simulation based obstacle-aware Steiner routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:385-388 [Conf]
  79. Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
    Timing-driven Steiner trees are (practically) free. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:389-392 [Conf]
  80. Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
    Systematic software-based self-test for pipelined processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:393-398 [Conf]
  81. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    A test pattern ordering algorithm for diagnosis with truncated fail data. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:399-404 [Conf]
  82. Ahmad A. Al-Yamani
    DFT for controlled-impedance I/O buffers. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:405-410 [Conf]
  83. Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
    Variation-aware analysis: savior of the nanometer era? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:411-412 [Conf]
  84. Hari Ananthan, Kaushik Roy
    A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:413-418 [Conf]
  85. Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
    A PLA based asynchronous micropipelining approach for subthreshold circuit design. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:419-424 [Conf]
  86. John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
    Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:425-428 [Conf]
  87. Huaizhi Wu, Martin D. F. Wong, I-Min Liu
    Timing-constrained and voltage-island-aware voltage assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:429-432 [Conf]
  88. Jason Cong, Zhiru Zhang
    An efficient and versatile scheduling algorithm based on SDC formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:433-438 [Conf]
  89. Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
    Register binding for clock period minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:439-444 [Conf]
  90. Ajay K. Verma, Paolo Ienne
    Towards the automatic exploration of arithmetic-circuit architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:445-450 [Conf]
  91. Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner
    Design space exploration using time and resource duality with the ant colony optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:451-454 [Conf]
  92. Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
    Rapid estimation of control delay from high-level specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:455-458 [Conf]
  93. J. Cohn, Jeong-Taek Kong, Chris Malachowsky, Rich Tobias, B. Traw
    Design challenges for next-generation multimedia, game and entertainment platforms. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:459- [Conf]
  94. Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi
    Architecture-aware FPGA placement using metric embedding. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:460-465 [Conf]
  95. Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
    Efficient SAT-based Boolean matching for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:466-471 [Conf]
  96. Joey Y. Lin, Deming Chen, Jason Cong
    Optimal simultaneous mapping and clustering for FPGA delay optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:472-477 [Conf]
  97. Yu Hu, Yan Lin, Lei He, Tim Tuan
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:478-483 [Conf]
  98. Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro
    VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:484-489 [Conf]
  99. Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
    A network security processor design based on an integrated SOC design and test platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:490-495 [Conf]
  100. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:496-501 [Conf]
  101. Roshan G. Ragel, Sri Parameswaran
    IMPRES: integrated monitoring for processor reliability and security. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:502-505 [Conf]
  102. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
    A parallelized way to provide data encryption and integrity checking on a processor-memory bus. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:506-509 [Conf]
  103. Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:510-515 [Conf]
  104. Kuo-Hua Wang
    Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:516-521 [Conf]
  105. Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
    Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:522-527 [Conf]
  106. Brian Swahn, Soha Hassoun
    Gate sizing: finFETs vs 32nm bulk MOSFETs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:528-531 [Conf]
  107. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    DAG-aware AIG rewriting a fresh look at combinational logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:532-535 [Conf]
  108. Björn Debaillie, Bruno Bougard, Gregory Lenoir, Gerd Vandersteen, Francky Catthoor
    Energy-scalable OFDM transmitter design and control. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:536-541 [Conf]
  109. Rajarshi Mukherjee, Seda Ogrenci Memik
    Systematic temperature sensor allocation and placement for microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:542-547 [Conf]
  110. Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha
    HybDTM: a coordinated hardware-software approach for dynamic thermal management. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:548-553 [Conf]
  111. Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
    A systematic method for functional unit power estimation in microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:554-557 [Conf]
  112. Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:558-561 [Conf]
  113. Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula
    Extending the lifetime of fuel cell based hybrid systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:562-567 [Conf]
  114. Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula
    High-level power management of embedded systems with application-specific energy cost functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:568-573 [Conf]
  115. Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng
    Communication latency aware low power NoC synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:574-579 [Conf]
  116. Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
    Optimality study of resource binding with multi-Vdds. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:580-585 [Conf]
  117. Lin Zhong, Bin Wei, Michael J. Sinclair
    SMERT: energy-efficient design of a multimedia messaging system for mobile devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:586-591 [Conf]
  118. Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu
    Signature-based workload estimation for mobile 3D graphics. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:592-597 [Conf]
  119. Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi
    Games are up for DVFS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:598-603 [Conf]
  120. Ali Iranli, Wonbok Lee, Massoud Pedram
    Backlight dimming in power-aware mobile displays. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:604-607 [Conf]
  121. Wei-Chung Cheng, Chain-Fu Chao
    Minimization for LED-backlit TFT-LCDs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:608-611 [Conf]
  122. Yan Meng, Timothy Sherwood, Ryan Kastner
    Leakage power reduction of embedded memories on FPGAs through location assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:612-617 [Conf]
  123. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias
    A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:618-623 [Conf]
  124. Georges Nabaa, Navid Azizi, Farid N. Najm
    An adaptive FPGA architecture with process variation compensation and reduced leakage. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:624-629 [Conf]
  125. Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
    FLAW: FPGA lifetime awareness. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:630-635 [Conf]
  126. Dean D. MacNeil, Edward H. Sargent
    Solution-processed infrared photovoltaic devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:636-638 [Conf]
  127. Rajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou
    Circuits for energy harvesting sensor signal processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:639-644 [Conf]
  128. Joseph A. Paradiso
    Systems for human-powered mobile computing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:645-650 [Conf]
  129. Aman Kansal, Jason Hsu, Mani B. Srivastava, Vijay Raghunathan
    Harvesting aware power management for sensor networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:651-656 [Conf]
  130. Jordi Cortadella, Michael Kishinevsky, Bill Grundmann
    Synthesis of synchronous elastic architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:657-662 [Conf]
  131. Sujan Pandey, Manfred Glesner
    Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:663-668 [Conf]
  132. Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
    Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:669-674 [Conf]
  133. Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
    Behavior and communication co-optimization for systems with sequential communication media. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:675-678 [Conf]
  134. Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
    Synthesis of high-performance packet processing pipelines. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:679-682 [Conf]
  135. Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya
    Buffer memory optimization for video codec application modeled in Simulink. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:689-694 [Conf]
  136. Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid
    Configurable cache subsetting for fast cache tuning. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:695-700 [Conf]
  137. Lei Yang, Haris Lekatsas, Robert P. Dick
    High-performance operating system controlled memory compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:701-704 [Conf]
  138. Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss
    A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:705-708 [Conf]
  139. Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini
    Tomorrow's analog: just dead or just different? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:709-710 [Conf]
  140. Wei Zhang, Niraj K. Jha, Li Shang
    NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:711-716 [Conf]
  141. Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
    Modeling and analysis of circuit performance of ballistic CNFET. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:717-722 [Conf]
  142. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Topology aware mapping of logic functions onto nanowire-based crossbar architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:723-726 [Conf]
  143. Reza M. Rad, Mohammad Tehranipoor
    A new hybrid FPGA with nanoscale clusters and CMOS routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:727-730 [Conf]
  144. Saurav Gorai, Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra
    Directed-simulation assisted formal verification of serial protocol and bridge. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:731-736 [Conf]
  145. Kuntal Nanshi, Fabio Somenzi
    Guiding simulation with increasingly refined abstract traces. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:737-742 [Conf]
  146. Weixin Wu, Michael S. Hsiao
    Mining global constraints for improving bounded sequential equivalence checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:743-748 [Conf]
  147. Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang
    An IC manufacturing yield model considering intra-die variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:749-754 [Conf]
  148. Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
    Novel full-chip gridless routing considering double-via insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:755-760 [Conf]
  149. Jia Wang, Hai Zhou
    Optimal jumper insertion for antenna avoidance under ratio upper-bound. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:761-766 [Conf]
  150. Natasa Miskov-Zivanov, Diana Marculescu
    MARS-C: modeling and reduction of soft errors in combinational circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:767-772 [Conf]
  151. Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
    A design approach for radiation-hard digital electronics. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:773-778 [Conf]
  152. Navid Azizi, Farid N. Najm
    A family of cells to reduce the soft-error-rate in ternary-CAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:779-784 [Conf]
  153. Peng Yu, Sean X. Shi, David Z. Pan
    Process variation aware OPC with variational lithography modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:785-790 [Conf]
  154. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
    Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:791-796 [Conf]
  155. Frank Huebbers, Ali Dasdan, Yehea I. Ismail
    Computation of accurate interconnect process parameter values for performance corners under process variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:797-800 [Conf]
  156. Ke Cao, Sorin Dobre, Jiang Hu
    Standard cell characterization considering lithography induced variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:801-804 [Conf]
  157. J. Bergeron, H. Foster, A. Piziali, R. S. Mitra, C. Ahlschlager, D. Stein
    Building a verification test plan: trading brute force for finesse. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:805-806 [Conf]
  158. Shekhar Borkar
    Electronics beyond nano-scale CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:807-808 [Conf]
  159. Kaustav Banerjee, Navin Srivastava
    Are carbon nanotubes the future of VLSI interconnections? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:809-814 [Conf]
  160. Erwin J. Prinz
    The zen of nonvolatile memories. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:815-820 [Conf]
  161. Ingo Pill, Simone Semprini, Roberto Cavada, Marco Roveri, Roderick Bloem, Alessandro Cimatti
    Formal analysis of hardware requirements. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:821-826 [Conf]
  162. Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta
    Test generation games from formal specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:827-832 [Conf]
  163. Lap-Fai Leung, Chi-Ying Tsui
    Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:833-838 [Conf]
  164. Ümit Y. Ogras, Radu Marculescu
    Prediction-based flow control for network-on-chip traffic. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:839-844 [Conf]
  165. Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli
    A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:845-848 [Conf]
  166. Ming Li, Qing-An Zeng, Wen-Ben Jone
    DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:849-852 [Conf]
  167. Kaushik Sheth, Egino Sarto, Joel McGrath
    The importance of adopting a package-aware chip design flow. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:853-856 [Conf]
  168. Chirag S. Patel
    Silicon carrier for computer systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:857-862 [Conf]
  169. Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann
    4.25 Gb/s laser driver: design challenges and EDA tool limitations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:863-866 [Conf]
  170. Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir
    Optimizing code parallelization through a constraint network based approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:863-688 [Conf]
  171. Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang
    Power-centric design of high-speed I/Os. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:867-872 [Conf]
  172. Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni
    A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:873-878 [Conf]
  173. Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud
    SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:879-884 [Conf]
  174. Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein
    Chameleon ART: a non-optimization based analog design migration framework. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:885-888 [Conf]
  175. Michaël Goffioul, Gerd Vandersteen, Joris Van Driessche, Björn Debaillie, Boris Come
    Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:889-892 [Conf]
  176. Chia-Jui Hsu, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, Shuvra S. Bhattacharyya
    Efficient simulation of critical synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:893-898 [Conf]
  177. Sander Stuijk, Marc Geilen, Twan Basten
    Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:899-904 [Conf]
  178. Wolfgang Klingauf, Robert Günzel, Oliver Bringmann, Pavel Parfuntseu, Mark Burton
    GreenBus: a generic interconnect fabric for transaction level modelling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:905-910 [Conf]
  179. F. Herrera, Eugenio Villar
    A framework for embedded system specification under different models of computation in SystemC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:911-914 [Conf]
  180. Elvinia Riccobene, Patrizia Scandurra, Alberto Rosti, Sara Bocchio
    A model-driven design environment for embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:915-918 [Conf]
  181. Constantin Pistol, Alvin R. Lebeck, Chris Dwyer
    Design automation for DNA self-assembled nanostructures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:919-924 [Conf]
  182. William L. Hwang, Fei Su, Krishnendu Chakrabarty
    Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:925-930 [Conf]
  183. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Placement of digital microfluidic biochips using the t-tree formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:931-934 [Conf]
  184. Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
    A high density, carbon nanotube capacitor for decoupling applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:935-938 [Conf]
  185. Josep Carmona, Jordi Cortadella
    State encoding of large asynchronous controllers. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:939-944 [Conf]
  186. Chuan Lin, Hai Zhou
    An efficient retiming algorithm under setup and hold constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:945-950 [Conf]
  187. Kui Wang, Lian Duan, Xu Cheng
    ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:951-954 [Conf]
  188. Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa
    Budgeting-free hierarchical design method for large scale and high-performance LSIs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:955-958 [Conf]
  189. Azadeh Davoodi, Ankur Srivastava
    Variability driven gate sizing for binning yield optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:959-964 [Conf]
  190. Quming Zhou, Kartik Mohanram
    Elmore model for energy estimation in RC trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:965-970 [Conf]
  191. Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy
    Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:971-976 [Conf]
  192. Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:977-982 [Conf]
  193. Saumil Shah, Puneet Gupta, Andrew B. Kahng
    Standard cell library optimization for leakage reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:983-986 [Conf]
  194. Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu
    Low-power bus encoding using an adaptive hybrid algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:987-990 [Conf]
  195. Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
    A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:991-996 [Conf]
  196. Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis
    Exploring compromises among timing, power and temperature in three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:997-1002 [Conf]
  197. Rui Shi, Chung-Kuan Cheng
    Efficient escape routing for hexagonal array of high density I/Os. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1003-1008 [Conf]
  198. Rohan Mandrekar, Krishna Bharath, Krishna Srinivasan, Ege Engin, Madhavan Swaminathan
    System level signal and power integrity analysis methodology for system-in-package applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1009-1012 [Conf]
  199. Wm. Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
    PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1013-1016 [Conf]
  200. Xiaolue Lai, Jaijeet S. Roychowdhury
    A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1017-1022 [Conf]
  201. Ying Wei, Alex Doboli
    Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1023-1028 [Conf]
  202. Ting Mei, Jaijeet S. Roychowdhury
    A robust envelope following method applicable to both non-autonomous and oscillatory circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1029-1034 [Conf]
  203. Guo Yu, Peng Li
    Lookup table based simulation and statistical modeling of Sigma-Delta ADCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1035-1040 [Conf]
  204. Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
    Clock buffer and wire sizing using sequential programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1041-1046 [Conf]
  205. Rakesh Vattikonda, Wenping Wang, Yu Cao
    Modeling and minimization of PMOS NBTI effect for robust nanometer design. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1047-1052 [Conf]
  206. Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala
    A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1053-1056 [Conf]
  207. Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge
    Reliability modeling and management in dynamic microprocessor-based systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1057-1060 [Conf]
  208. Shishpal Rawat, Raul Camposano, A. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, A. Sharan
    DFM: where's the proof of value? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1061-1062 [Conf]
  209. Xiushan Feng, Alan J. Hu
    Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1063-1068 [Conf]
  210. Guy Dupenloup, Thierry Lemeunier, Roland Mayr
    Transistor abstraction for the functional verification of FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1069-1072 [Conf]
  211. Mohammad Awedh, Fabio Somenzi
    Automatic invariant strengthening to prove properties in bounded model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1073-1076 [Conf]
  212. Prakash M. Peranandam, Pradeep K. Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel
    Fast falsification based on symbolic bounded property checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1077-1082 [Conf]
  213. Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wen-Long Wei
    Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1083-1088 [Conf]
  214. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Test response compactor with programmable selector. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1089-1094 [Conf]
  215. Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
    Fault detection and diagnosis with parity trees for space compaction of test responses. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1095-1098 [Conf]
  216. Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton
    Multiple-detect ATPG based on physical neighborhoods. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1099-1102 [Conf]
  217. Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack
    Constraint-driven floorplan repair. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1103-1108 [Conf]
  218. Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu
    Optimal cell flipping in placement and floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1109-1114 [Conf]
  219. Tao Luo, David Newmark, David Z. Pan
    A new LP based incremental timing driven placement for high performance designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1115-1120 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002