Conferences in DBLP
Robert Dahlberg , Kurt Keutzer , R. Bingham , Aart J. de Geus , Walden C. Rhines EDA: this is serious business. [Citation Graph (0, 0)][DBLP ] Conf ] Arman Vassighi , Ali Keshavarzi , Siva Narendra , Gerhard Schrom , Yibin Ye , Seri Lee , Greg Chrysler , Manoj Sachdev , Vivek De Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Agarwal , Chris H. Kim , Saibal Mukhopadhyay , Kaushik Roy Leakage in nano-scale technologies: mechanisms, impact and design considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Lei He , Weiping Liao , Mircea R. Stan System level leakage reduction considering the interdependence of temperature and leakage. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Rajaram , Jiang Hu , Rabi N. Mahapatra Reducing clock skew variability via cross links. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Milos Hrkic , Jiang Hu , Stephen T. Quay Fast and flexible buffer trees that navigate the physical layout environment. [Citation Graph (0, 0)][DBLP ] Conf ] Xun Liu , Yuantao Peng , Marios C. Papaefthymiou Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP ] Conf ] Michael L. Behm , John M. Ludden , Yossi Lichtenstein , Michal Rimon , Michael Vinov Industrial experience with test generation languages for processor verification. [Citation Graph (0, 0)][DBLP ] Conf ] Sigal Asaf , Eitan Marcus , Avi Ziv Defining coverage views to improve functional coverage analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Su Kwon , Young-Il Kim , Chong-Min Kyung Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. [Citation Graph (0, 0)][DBLP ] Conf ] Shai Fine , Shmuel Ur , Avi Ziv Probabilistic regression suites for functional verification. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel L. Rosenband , Arvind Modular scheduling of guarded atomic actions. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Kapp , Viktor K. Sabelfeld Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Robert K. Brayton A timing-driven module-based chip design flow. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Edman , Christer Svensson Timing closure through a globally synchronous, timing partitioned design methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Shekhar Borkar , Tanay Karnik , Vivek De Design and reliability challenges in nanometer technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh R. Shanbhag A communication-theoretic design paradigm for reliable SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni De Micheli Reliable communication in systems on chips. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin Designing robust microarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar K. Iyer Hierarchical application aware error detection and recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas J. Strojwas , Michael Campbell , Vassilios Gerousis , Jim Hogan , John Kibarian , Marc Levitt , Walter Ng , Dipu Pramanik , Mark Templeton When IC yield missed the target, who is at fault? [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Gi Lyuh , Taewhan Kim Memory access scheduling and binding considering energy minimization in multi-bank memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Seo , Taewhan Kim , Ki-Seok Chung Profile-based optimal intra-task voltage scheduling for hard real-time applications. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Antonio Carballo , Kevin J. Nowka , Seung-Moon Yoo , Ivan Vo , Clay Cranford , V. Robert Norman Requirement-based design methods for adaptive communications links. [Citation Graph (0, 0)][DBLP ] Conf ] Anish Muttreja , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha Automated energy/performance macromodeling of embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasa R. Sridhara , Naresh R. Shanbhag Coding for system-on-chip networks: a unified framework. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Schüle , Klaus Schneider Abstraction of assembler programs for symbolic worst case execution time analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Nikil D. Dutt , Mohamed Ben-Romdhane Extending the transaction level modeling approach for fast communication architecture exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Resano , Daniel Mozos Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir LODS: locality-oriented dynamic scheduling for on-chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Brandolese , William Fornaciari , Fabio Salice An area estimation methodology for FPGA based designs at systemc-level. [Citation Graph (0, 0)][DBLP ] Conf ] Johan P. Vanderhaegen , Robert W. Brodersen Automated design of operational transconductance amplifiers using reversed geometric programming. [Citation Graph (0, 0)][DBLP ] Conf ] Sambuddha Bhattacharya , Nuttorn Jangkrajarng , Roy Hartono , C.-J. Richard Shi Correct-by-construction layout-centric retargeting of large analog designs. [Citation Graph (0, 0)][DBLP ] Conf ] Anuradha Agarwal , Hemanth Sampath , Veena Yelamanchili , Ranga Vemuri Fast and accurate parasitic capacitance models for layout-aware. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Xu , Lawrence T. Pileggi , Stephen P. Boyd ORACLE: optimization with recourse of analog circuits including layout extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Zhang , E. Aykut Dengi , Ronald A. Rohrer , Rob A. Rutenbar , L. Richard Carley A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Wang , Malgorzata Marek-Sadowska Buffer sizing for clock power minimization subject to general skew constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Min Zhao , Yuhong Fu , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda Optimal placement of power supply pads and pins. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Pant , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda A stochastic approach To power grid analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Su-Wei Wu , Yao-Wen Chang Efficient power/ground network analysis for power integrity-driven design methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Goeran Jerke , Jens Lienig , Jürgen Scheible Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs. [Citation Graph (0, 0)][DBLP ] Conf ] Nitin Deo , Behrooz Zahiri , Ivo Bolsens , Jason Cong , Bhusan Gupta , Philip Lopresti , Christopher B. Reynolds , Chris Rowen , Ray Simar What happened to ASIC?: Go (recon)figure? [Citation Graph (0, 0)][DBLP ] Conf ] Li-Da Huang , Martin D. F. Wong Optical proximity correction (OPC): friendly maze routing. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Jamil Kawa , Raul Camposano Design automation for mask programmable fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Yajun Ran , Malgorzata Marek-Sadowska On designing via-configurable cell blocks for regular fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] V. Kheterpal , Andrzej J. Strojwas , Lawrence T. Pileggi Routing architecture exploration for regular fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Yoshida , Kaushik De , Vamsi Boppana Accurate pre-layout estimation of standard cell characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Ganapathy Parthasarathy , Madhu K. Iyer , Kwang-Ting Cheng , Li-C. Wang An efficient finite-domain constraint solver for circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zaher S. Andraus , Karem A. Sakallah Automatic abstraction and verification of verilog models. [Citation Graph (0, 0)][DBLP ] Conf ] Freddy Y. C. Mang , Pei-Hsin Ho Abstraction refinement by controllability and cooperativeness analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Lu , Mike Jorda Verifying a gigabit ethernet switch using SMV. [Citation Graph (0, 0)][DBLP ] Conf ] Hazem I. Shehata , Mark Aagaard A general decomposition strategy for verifying register renaming. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Poletti , Paul Marchal , David Atienza , Luca Benini , Francky Catthoor , Jose Manuel Mendias An integrated hardware/software approach for run-time scratchpad management. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo Wanderley Netto , Rodolfo Azevedo , Paulo Centoducatte , Guido Araujo Multi-profile based code compression. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Il Han , Amer Baghdadi , Marius Bonaciu , Soo-Ik Chae , Ahmed Amine Jerraya An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Nollet , Théodore Marescaux , Diederik Verkest , Jean-Yves Mignolet , Serge Vernalde Operating-system controlled network on chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jingcao Hu , Radu Marculescu DyAD: smart routing for networks-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen Sentovich , Raul Camposano , Jim Douglas , Aurangzeb Khan Business models in IP, software licensing, and services. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen Sentovich , Jaswinder Ahuja , Paul Lippe , Bernie Rosenthal Competitive strategies for the electronics industry. [Citation Graph (0, 0)][DBLP ] Conf ] David S. Kung Timing closure for low-FO4 microprocessor design. [Citation Graph (0, 0)][DBLP ] Conf ] Paul K. Rodman Forest vs. trees: where's the slack? [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Vujkovic , David Wadkins , William Swartz , Carl Sechen Efficient timing closure without timing driven placement and routing. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Robert F. Damiano , Bob Bentley , Kurt Baty , Kevin Normoyle , Makoto Ishii , Einat Yogev Verification: what works and what doesn't. [Citation Graph (0, 0)][DBLP ] Conf ] Ravindra Jejurikar , Cristiano Pereira , Rajesh K. Gupta Leakage aware dynamic voltage scaling for real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lukai Cai , Andreas Gerstlauer , Daniel Gajski Retargetable profiling for rapid, early system-level design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua J. Pieper , Alain Mellan , JoAnn M. Paul , Donald E. Thomas , Faraydon Karim High level cache simulation for heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Il Kim , Woo-Seung Yang , Young-Su Kwon , Chong-Min Kyung Communication-efficient hardware acceleration for fast functional simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichi Nakamura , Kouhei Hosokawa , Ichiro Kuroda , Ko Yoshikawa , Takeshi Yoshimura A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. [Citation Graph (0, 0)][DBLP ] Conf ] Seokwoo Lee , Shidhartha Das , Valeria Bertacco , Todd M. Austin , David Blaauw , Trevor N. Mudge Circuit-aware architectural simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Capodieci , Puneet Gupta , Andrew B. Kahng , Dennis Sylvester , Jie Yang Toward a methodology for manufacturability-driven design rule exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin W. McCullen Phase correct routing for alternating phase shift masks. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Fook-Luen Heng Toward a systematic-variation aware timing methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Puneet Sharma , Dennis Sylvester Selective gate-length biasing for cost-effective runtime leakage control. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Visweswariah , K. Ravindran , K. Kalafala , Steven G. Walker , S. Narayan First-order incremental block-based statistical timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Orshansky , Arnab Bandyopadhyay Fast statistical timing analysis handling arbitrary delay correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Jiayong Le , Xin Li , Lawrence T. Pileggi STAC: statistical timing analysis with correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Pierre G. Paulin , Reinaldo A. Bergamaschi , Raj Pawate , Arie Bernstein , Ramesh Chandra , Mohamed Ben-Romdhane System level design: six success stories in search of an industry. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong Xiu , James D. Z. Ma , Suzanne M. Fowler , Rob A. Rutenbar Large-scale placement by grid-warping. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sherief Reda Placement feedback: a concept and method for better min-cut placements. [Citation Graph (0, 0)][DBLP ] Conf ] Dominic A. Antonelli , Danny Z. Chen , Timothy J. Dysart , Xiaobo Sharon Hu , Andrew B. Kahng , Peter M. Kogge , Richard C. Murphy , Michael T. Niemier Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Ngai Wong , Venkataramanan Balakrishnan , Cheng-Kok Koh Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Janet Meiling Wang , Omar Hafiz , Jun Li A linear fractional transform (LFT) based model for interconnect parametric uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani R. Nassif , Sarma B. K. Vrudhula Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Miguel Silveira , Joel R. Phillips Exploiting input information in a model reduction algorithm for massively coupled parasitic networks. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Mittal , David Zaretsky , Xiaoyong Tang , Prithviraj Banerjee Automatic translation of software binaries onto FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Brisk , Adam Kaplan , Majid Sarrafzadeh Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir , I. Demirkiran , Guangyu Chen , Mary Jane Irwin Data compression for improving SPM behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Gary Smith Platform based design: does it answer the entire SoC challenge? [Citation Graph (0, 0)][DBLP ] Conf ] Mark Hopkins Nomadic platform approach for wireless mobile multimedia. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli , Luca P. Carloni , Fernando De Bernardinis , Marco Sgroi Benefits and challenges for platform-based design. [Citation Graph (0, 0)][DBLP ] Conf ] Max Baron Trends in the use of re-configurable platforms. [Citation Graph (0, 0)][DBLP ] Conf ] David Bañeres , Jordi Cortadella , Michael Kishinevsky A recursive paradigm to solve Boolean relations. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Saluja , Sunil P. Khatri A robust algorithm for approximate compatible observability don't care (CODC) computation. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Munehiro Matsuura A method to decompose multiple-output logic functions. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hua Wang , Jia-Hung Chen Symmetry detection for incompletely specified functions. [Citation Graph (0, 0)][DBLP ] Conf ] Victor N. Kravets , Prabhakar Kudva Implicit enumeration of structural changes in circuit optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev R. Rao , Anirudh Devgan , David Blaauw , Dennis Sylvester Parametric yield estimation considering leakage variability. [Citation Graph (0, 0)][DBLP ] Conf ] Sreeja Raj , Sarma B. K. Vrudhula , Janet Meiling Wang A methodology to improve timing yield in the presence of process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Hoon Choi , Bipul Chandra Paul , Kaushik Roy Novel sizing algorithm for yield improvement under process variation in nanometer technology. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm , Noel Menezes Statistical timing analysis based on a timing yield model. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit K. Deb , Axel Jantsch , Johnny Öberg System design for DSP applications in transaction level modeling paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Wu , Jianwen Zhu , Farid N. Najm An analytical approach for dynamic range estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Changchun Shi , Robert W. Brodersen Automated fixed-point data-type optimization tool for signal processing and communication systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sanghamitra Roy , Prithviraj Banerjee An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. [Citation Graph (0, 0)][DBLP ] Conf ] Marghoob Mohiyuddin , Amit Prakash , Adnan Aziz , Wayne Wolf Synthesizing interconnect-efficient low density parity check codes. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , T. M. Mak , Kwang-Ting Cheng , Magdy S. Abadir On path-based learning and its applications in delay test and diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Verma , Shantanu Dutt , Vishal Suthar Efficient on-line testing of FPGAs with provable diagnosabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Goldman , Kurt Keutzer , Clive Bittlestone , Ahsan Bootehsaz , Shekhar Y. Borkar , E. Chen , Louis Scheffer , Chandramouli Visweswariah Is statistical timing statistically significant? [Citation Graph (0, 0)][DBLP ] Conf ] Wei Li , Sudhakar M. Reddy , Irith Pomeranz On test generation for transition faults with minimized peak power dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Sungju Park , Sangwook Cho , Seiyang Yang , Maciej J. Ciesielski A new state assignment technique for testing and low power. [Citation Graph (0, 0)][DBLP ] Conf ] Bart Vermeulen , Mohammad Z. Urfianto , Sandeep Kumar Goel Automatic generation of breakpoint hardware for silicon debug. [Citation Graph (0, 0)][DBLP ] Conf ] Yoonna Oh , Maher N. Mneimneh , Zaher S. Andraus , Karem A. Sakallah , Igor L. Markov AMUSE: a minimally-unsatisfiable subformula extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Pankaj Chauhan , Edmund M. Clarke , Daniel Kroening A SAT-based algorithm for reparameterization in symbolic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Paul T. Darga , Mark H. Liffiton , Karem A. Sakallah , Igor L. Markov Exploiting structure in symmetry detection for CNF. [Citation Graph (0, 0)][DBLP ] Conf ] Chao Wang , HoonSang Jin , Gary D. Hachtel , Fabio Somenzi Refining the SAT decision ordering for bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Demos Anastasakis , Lisa McIlwain , Slawomir Pilarski Efficient equivalence checking with partitions and hierarchical cut-points. [Citation Graph (0, 0)][DBLP ] Conf ] Shishpal Rawat , William H. Joyner Jr. , John A. Darringer , Daniel Gajski , Pat O. Pistilli , Hugo De Man , Carl Harris , James Solomon Were the good old days all that good?: EDA then and now. [Citation Graph (0, 0)][DBLP ] Conf ] Kihwan Choi , Ramakrishna Soma , Massoud Pedram Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Zhang , Robert P. Dick , Krishnendu Chakrabarty Energy-aware deterministic fault tolerance in distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Kejariwal , Sumit Gupta , Alexandru Nicolau , Nikil Dutt , Rajesh Gupta Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoping Hu , Radu Marculescu Adaptive data partitioning for ambient multimedia. [Citation Graph (0, 0)][DBLP ] Conf ] Siddharth Choudhuri , Rabi N. Mahapatra Energy characterization of filesystems for diskless embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vidyasagar Nookala , Sachin S. Sapatnekar A method for correcting the functionality of a wire-pipelined circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Mario R. Casu , Luca Macchiarulo A new approach to latency insensitive design. [Citation Graph (0, 0)][DBLP ] Conf ] Qinghua Liu , Malgorzata Marek-Sadowska Pre-layout wire length and congestion estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Davare , Kelvin Lwin , Alex Kondratyev , Alberto L. Sangiovanni-Vincentelli The best of both worlds: the efficient asynchronous implementation of synchronous specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Cheoljoo Jeong , Steven M. Nowick Fast hazard detection in combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Margarida F. Jacome , Chen He , Gustavo de Veciana , Stephen Bijansky Defect tolerant probabilistic design paradigm for nanotechnologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yiping Fan , Zhiru Zhang Architecture-level synthesis for automatic interconnect pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Samar Abdi , Daniel Gajski Automatic generation of equivalent architecture model from functional specification. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Yang , Ramesh Karri , David A. McGrew Divide-and-concatenate: an architecture level optimization technique for universal hash functions. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Conti , Marco Caldari , Giovanni B. Vece , Simone Orcioni , Claudio Turchetti Performance analysis of different arbitration algorithms of the AMBA AHB bus. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Korsmeyer , Jun Zeng , Ken Greiner Design tools for BioMEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob White CAD challenges in BioMEMS design. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , Tony Bonaccio , Teresa H. Y. Meng , Ernesto Perea , Robert Pitts , Charles Sodini , Jim Wieser Will Moore's Law rule in the land of analog? [Citation Graph (0, 0)][DBLP ] Conf ] Mongkol Ekpanyapong , Jacob R. Minz , Thaisiri Watewai , Hsien-Hsin S. Lee , Sung Kyu Lim Profile-guided microarchitectural floorplanning for deep submicron processor design. [Citation Graph (0, 0)][DBLP ] Conf ] Changbo Long , Lucanus Simonson , Weiping Liao , Lei He Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Li , Tan Yan , Bo Yang , Juebang Yu , Chunhui Li A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation. [Citation Graph (0, 0)][DBLP ] Conf ] Dionysios Kouroussis , Rubil Ahmadi , Farid N. Najm Worst-case circuit delay taking into account power supply variations. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Agarwal , Florentin Dartu , David Blaauw Statistical gate delay model considering multiple input switching. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Lee , Vladimir Zolotov , David Blaauw Static timing analysis using backward signal propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim G. Clabes , Joshua Friedrich , Mark Sweet , Jack DiLullo , Sam Chu , Donald Plass , James Dawson , Paul Muench , Larry Powell , Michael S. Floyd , Balaram Sinharoy , Mike Lee , Michael Goulet , James Wagoner , Nicole Schwartz , Stephen L. Runyon , Gary Gorman , Phillip Restle , Ronald N. Kalla , Joseph McGill , Steve Dodson Design and implementation of the POWER5 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinari Takayanagi , Jinuk Luke Shin , Bruce Petrick , Jeffrey Su , Ana Sonia Leon A dual-core 64b ultraSPARC microprocessor for dense server applications. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel J. Deleganes , Micah Barany , George Geannopoulos , Kurt Kreitzer , Anant P. Singh , Sapumal Wijeratne Low voltage swing logic circuits for a Pentium 4 processor integer core. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf The future of multiprocessor systems-on-chips. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Kogel , Heinrich Meyr Heterogeneous MP-SoC: the solution to energy-efficient signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Rowen , Steve Leibson Flexible architectures for engineering successful SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Saxena , Bill Halpin Modeling repeaters explicitly within analytical placement. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Obermeier , Frank M. Johannes Quadratic placement using an improved timing model. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Hrkic , John Lillis , Giancarlo Beraudo An approach to placement-coupled logic replication. [Citation Graph (0, 0)][DBLP ] Conf ] Gunnar Braun , Achim Nohl , Weihua Sheng , Jianjiang Ceng , Manuel Hohenauer , Hanno Scharwächter , Rainer Leupers , Heinrich Meyr A novel approach for flexible and consistent ADL-driven ASIP design. [Citation Graph (0, 0)][DBLP ] Conf ] Pan Yu , Tulika Mitra Characterizing embedded applications for instruction-set extensible processors. [Citation Graph (0, 0)][DBLP ] Conf ] Partha Biswas , Vinay Choudhary , Kubilay Atasu , Laura Pozzi , Paolo Ienne , Nikil Dutt Introduction of local memory elements in instruction set extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Li , Yan Lin , Lei He FPGA power reduction using configurable dual-Vdd. [Citation Graph (0, 0)][DBLP ] Conf ] Navaratnasothie Selvakkumaran , Abhishek Ranjan , Salil Raje , George Karypis Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuyuki Ohba , Kohji Takano An SoC design methodology using FPGAs and embedded microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Paul C. Kocher , Ruby B. Lee , Gary McGraw , Anand Raghunathan Security as a new dimension in embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Kumar Sultania , Dennis Sylvester , Sachin S. Sapatnekar Tradeoffs between date oxide leakage and delay for dual Tox circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kaviraj Chopra , Sarma B. K. Vrudhula Implicit pseudo boolean enumeration algorithms for input vector control. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Srivastava , Dennis Sylvester , David Blaauw Statistical optimization of leakage power considering process variations using dual-Vth and sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Harmander Deogun , Rajeev R. Rao , Dennis Sylvester , David Blaauw Leakage-and crosstalk-aware bus encoding for total power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Srivastava , Dennis Sylvester , David Blaauw Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Shu Yan , Vivek Sarin , Weiping Shi Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. [Citation Graph (0, 0)][DBLP ] Conf ] Dipanjan Gope , Swagato Chakraborty , Vikram Jandhyala A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Satrajit Gupta , Lawrence T. Pileggi CHIME: coupled hierarchical inductance model evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Kapur , David E. Long Large-scale full-wave simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichi Tanji , Hideki Asai Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , Cheng-Tao Hsieh , Kai-Chiang Wu Re-synthesis for delay variation tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Aiqun Cao , Cheng-Kok Koh Post-layout logic optimization of domino circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Tummeltshammer , James C. Hoe , Markus Püschel Multiple constant multiplication by time-multiplexed mapping of addition chains. [Citation Graph (0, 0)][DBLP ] Conf ] Hemangee K. Kapoor , Mark B. Josephs Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Kerntopf A new heuristic algorithm for reversible logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] William N. N. Hung , Xiaoyu Song , Guowu Yang , Jin Yang , Marek A. Perkowski Quantum logic synthesis by symbolic reachability analysis. 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