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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2004 (conf/dac/2004)

  1. Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines
    EDA: this is serious business. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:1- [Conf]
  2. Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
    Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:2-5 [Conf]
  3. Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
    Leakage in nano-scale technologies: mechanisms, impact and design considerations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:6-11 [Conf]
  4. Lei He, Weiping Liao, Mircea R. Stan
    System level leakage reduction considering the interdependence of temperature and leakage. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:12-17 [Conf]
  5. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
    Reducing clock skew variability via cross links. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:18-23 [Conf]
  6. Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Fast and flexible buffer trees that navigate the physical layout environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:24-29 [Conf]
  7. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:30-35 [Conf]
  8. Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov
    Industrial experience with test generation languages for processor verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:36-40 [Conf]
  9. Sigal Asaf, Eitan Marcus, Avi Ziv
    Defining coverage views to improve functional coverage analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:41-44 [Conf]
  10. Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
    Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:45-48 [Conf]
  11. Shai Fine, Shmuel Ur, Avi Ziv
    Probabilistic regression suites for functional verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:49-54 [Conf]
  12. Daniel L. Rosenband, Arvind
    Modular scheduling of guarded atomic actions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:55-60 [Conf]
  13. Kai Kapp, Viktor K. Sabelfeld
    Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:61-66 [Conf]
  14. Fan Mo, Robert K. Brayton
    A timing-driven module-based chip design flow. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:67-70 [Conf]
  15. Anders Edman, Christer Svensson
    Timing closure through a globally synchronous, timing partitioned design methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:71-74 [Conf]
  16. Shekhar Borkar, Tanay Karnik, Vivek De
    Design and reliability challenges in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:75- [Conf]
  17. Naresh R. Shanbhag
    A communication-theoretic design paradigm for reliable SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:76- [Conf]
  18. Giovanni De Micheli
    Reliable communication in systems on chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:77- [Conf]
  19. Todd M. Austin
    Designing robust microarchitectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:78- [Conf]
  20. Ravishankar K. Iyer
    Hierarchical application aware error detection and recovery. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:79- [Conf]
  21. Andreas J. Strojwas, Michael Campbell, Vassilios Gerousis, Jim Hogan, John Kibarian, Marc Levitt, Walter Ng, Dipu Pramanik, Mark Templeton
    When IC yield missed the target, who is at fault? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:80- [Conf]
  22. Chun-Gi Lyuh, Taewhan Kim
    Memory access scheduling and binding considering energy minimization in multi-bank memory systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:81-86 [Conf]
  23. Jaewon Seo, Taewhan Kim, Ki-Seok Chung
    Profile-based optimal intra-task voltage scheduling for hard real-time applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:87-92 [Conf]
  24. Juan Antonio Carballo, Kevin J. Nowka, Seung-Moon Yoo, Ivan Vo, Clay Cranford, V. Robert Norman
    Requirement-based design methods for adaptive communications links. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:93-98 [Conf]
  25. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Automated energy/performance macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:99-102 [Conf]
  26. Srinivasa R. Sridhara, Naresh R. Shanbhag
    Coding for system-on-chip networks: a unified framework. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:103-106 [Conf]
  27. Tobias Schüle, Klaus Schneider
    Abstraction of assembler programs for symbolic worst case execution time analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:107-112 [Conf]
  28. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Extending the transaction level modeling approach for fast communication architecture exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:113-118 [Conf]
  29. Javier Resano, Daniel Mozos
    Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:119-124 [Conf]
  30. Mahmut T. Kandemir
    LODS: locality-oriented dynamic scheduling for on-chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:125-128 [Conf]
  31. Carlo Brandolese, William Fornaciari, Fabio Salice
    An area estimation methodology for FPGA based designs at systemc-level. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:129-132 [Conf]
  32. Johan P. Vanderhaegen, Robert W. Brodersen
    Automated design of operational transconductance amplifiers using reversed geometric programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:133-138 [Conf]
  33. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
    Correct-by-construction layout-centric retargeting of large analog designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:139-144 [Conf]
  34. Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
    Fast and accurate parasitic capacitance models for layout-aware. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:145-150 [Conf]
  35. Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
    ORACLE: optimization with recourse of analog circuits including layout extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:151-154 [Conf]
  36. Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley
    A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:155-158 [Conf]
  37. Kai Wang, Malgorzata Marek-Sadowska
    Buffer sizing for clock power minimization subject to general skew constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:159-164 [Conf]
  38. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Optimal placement of power supply pads and pins. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:165-170 [Conf]
  39. Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    A stochastic approach To power grid analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:171-176 [Conf]
  40. Su-Wei Wu, Yao-Wen Chang
    Efficient power/ground network analysis for power integrity-driven design methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:177-180 [Conf]
  41. Goeran Jerke, Jens Lienig, Jürgen Scheible
    Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:181-184 [Conf]
  42. Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar
    What happened to ASIC?: Go (recon)figure? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:185- [Conf]
  43. Li-Da Huang, Martin D. F. Wong
    Optical proximity correction (OPC): friendly maze routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:186-191 [Conf]
  44. Narendra V. Shenoy, Jamil Kawa, Raul Camposano
    Design automation for mask programmable fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:192-197 [Conf]
  45. Yajun Ran, Malgorzata Marek-Sadowska
    On designing via-configurable cell blocks for regular fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:198-203 [Conf]
  46. V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
    Routing architecture exploration for regular fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:204-207 [Conf]
  47. Hiroaki Yoshida, Kaushik De, Vamsi Boppana
    Accurate pre-layout estimation of standard cell characteristics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:208-211 [Conf]
  48. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    An efficient finite-domain constraint solver for circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:212-217 [Conf]
  49. Zaher S. Andraus, Karem A. Sakallah
    Automatic abstraction and verification of verilog models. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:218-223 [Conf]
  50. Freddy Y. C. Mang, Pei-Hsin Ho
    Abstraction refinement by controllability and cooperativeness analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:224-229 [Conf]
  51. Yuan Lu, Mike Jorda
    Verifying a gigabit ethernet switch using SMV. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:230-233 [Conf]
  52. Hazem I. Shehata, Mark Aagaard
    A general decomposition strategy for verifying register renaming. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:234-237 [Conf]
  53. Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias
    An integrated hardware/software approach for run-time scratchpad management. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:238-243 [Conf]
  54. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-profile based code compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:244-249 [Conf]
  55. Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya
    An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:250-255 [Conf]
  56. Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde
    Operating-system controlled network on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:256-259 [Conf]
  57. Jingcao Hu, Radu Marculescu
    DyAD: smart routing for networks-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:260-263 [Conf]
  58. Ellen Sentovich, Raul Camposano, Jim Douglas, Aurangzeb Khan
    Business models in IP, software licensing, and services. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:264- [Conf]
  59. Ellen Sentovich, Jaswinder Ahuja, Paul Lippe, Bernie Rosenthal
    Competitive strategies for the electronics industry. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:264- [Conf]
  60. David S. Kung
    Timing closure for low-FO4 microprocessor design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:265-266 [Conf]
  61. Paul K. Rodman
    Forest vs. trees: where's the slack? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:267- [Conf]
  62. Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen
    Efficient timing closure without timing driven placement and routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:268-273 [Conf]
  63. Francine Bacchini, Robert F. Damiano, Bob Bentley, Kurt Baty, Kevin Normoyle, Makoto Ishii, Einat Yogev
    Verification: what works and what doesn't. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:274- [Conf]
  64. Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta
    Leakage aware dynamic voltage scaling for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:275-280 [Conf]
  65. Lukai Cai, Andreas Gerstlauer, Daniel Gajski
    Retargetable profiling for rapid, early system-level design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:281-286 [Conf]
  66. Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim
    High level cache simulation for heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:287-292 [Conf]
  67. Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung
    Communication-efficient hardware acceleration for fast functional simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:293-298 [Conf]
  68. Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura
    A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:299-304 [Conf]
  69. Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Circuit-aware architectural simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:305-310 [Conf]
  70. Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Toward a methodology for manufacturability-driven design rule exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:311-316 [Conf]
  71. Kevin W. McCullen
    Phase correct routing for alternating phase shift masks. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:317-320 [Conf]
  72. Puneet Gupta, Fook-Luen Heng
    Toward a systematic-variation aware timing methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:321-326 [Conf]
  73. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Selective gate-length biasing for cost-effective runtime leakage control. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:327-330 [Conf]
  74. Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan
    First-order incremental block-based statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:331-336 [Conf]
  75. Michael Orshansky, Arnab Bandyopadhyay
    Fast statistical timing analysis handling arbitrary delay correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:337-342 [Conf]
  76. Jiayong Le, Xin Li, Lawrence T. Pileggi
    STAC: statistical timing analysis with correlation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:343-348 [Conf]
  77. Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane
    System level design: six success stories in search of an industry. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:349-350 [Conf]
  78. Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar
    Large-scale placement by grid-warping. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:351-356 [Conf]
  79. Andrew B. Kahng, Sherief Reda
    Placement feedback: a concept and method for better min-cut placements. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:357-362 [Conf]
  80. Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier
    Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:363-368 [Conf]
  81. Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:369-374 [Conf]
  82. Janet Meiling Wang, Omar Hafiz, Jun Li
    A linear fractional transform (LFT) based model for interconnect parametric uncertainty. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:375-380 [Conf]
  83. Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
    Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:381-384 [Conf]
  84. Luis Miguel Silveira, Joel R. Phillips
    Exploiting input information in a model reduction algorithm for massively coupled parasitic networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:385-388 [Conf]
  85. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
    Automatic translation of software binaries onto FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:389-394 [Conf]
  86. Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
    Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:395-400 [Conf]
  87. Ozcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, Guangyu Chen, Mary Jane Irwin
    Data compression for improving SPM behavior. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:401-406 [Conf]
  88. Gary Smith
    Platform based design: does it answer the entire SoC challenge? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:407- [Conf]
  89. Mark Hopkins
    Nomadic platform approach for wireless mobile multimedia. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:408- [Conf]
  90. Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Fernando De Bernardinis, Marco Sgroi
    Benefits and challenges for platform-based design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:409-414 [Conf]
  91. Max Baron
    Trends in the use of re-configurable platforms. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:415- [Conf]
  92. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    A recursive paradigm to solve Boolean relations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:416-421 [Conf]
  93. Nikhil Saluja, Sunil P. Khatri
    A robust algorithm for approximate compatible observability don't care (CODC) computation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:422-427 [Conf]
  94. Tsutomu Sasao, Munehiro Matsuura
    A method to decompose multiple-output logic functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:428-433 [Conf]
  95. Kuo-Hua Wang, Jia-Hung Chen
    Symmetry detection for incompletely specified functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:434-437 [Conf]
  96. Victor N. Kravets, Prabhakar Kudva
    Implicit enumeration of structural changes in circuit optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:438-441 [Conf]
  97. Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
    Parametric yield estimation considering leakage variability. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:442-447 [Conf]
  98. Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang
    A methodology to improve timing yield in the presence of process variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:448-453 [Conf]
  99. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Novel sizing algorithm for yield improvement under process variation in nanometer technology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:454-459 [Conf]
  100. Farid N. Najm, Noel Menezes
    Statistical timing analysis based on a timing yield model. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:460-465 [Conf]
  101. Abhijit K. Deb, Axel Jantsch, Johnny Öberg
    System design for DSP applications in transaction level modeling paradigm. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:466-471 [Conf]
  102. Bin Wu, Jianwen Zhu, Farid N. Najm
    An analytical approach for dynamic range estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:472-477 [Conf]
  103. Changchun Shi, Robert W. Brodersen
    Automated fixed-point data-type optimization tool for signal processing and communication systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:478-483 [Conf]
  104. Sanghamitra Roy, Prithviraj Banerjee
    An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:484-487 [Conf]
  105. Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne Wolf
    Synthesizing interconnect-efficient low density parity check codes. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:488-491 [Conf]
  106. Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
    On path-based learning and its applications in delay test and diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:492-497 [Conf]
  107. Vinay Verma, Shantanu Dutt, Vishal Suthar
    Efficient on-line testing of FPGAs with provable diagnosabilities. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:498-503 [Conf]
  108. Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
    Is statistical timing statistically significant? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:498- [Conf]
  109. Wei Li, Sudhakar M. Reddy, Irith Pomeranz
    On test generation for transition faults with minimized peak power dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:504-509 [Conf]
  110. Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski
    A new state assignment technique for testing and low power. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:510-513 [Conf]
  111. Bart Vermeulen, Mohammad Z. Urfianto, Sandeep Kumar Goel
    Automatic generation of breakpoint hardware for silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:514-517 [Conf]
  112. Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov
    AMUSE: a minimally-unsatisfiable subformula extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:518-523 [Conf]
  113. Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
    A SAT-based algorithm for reparameterization in symbolic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:524-529 [Conf]
  114. Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov
    Exploiting structure in symmetry detection for CNF. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:530-534 [Conf]
  115. Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
    Refining the SAT decision ordering for bounded model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:535-538 [Conf]
  116. Demos Anastasakis, Lisa McIlwain, Slawomir Pilarski
    Efficient equivalence checking with partitions and hierarchical cut-points. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:539-542 [Conf]
  117. Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon
    Were the good old days all that good?: EDA then and now. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:543- [Conf]
  118. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:544-549 [Conf]
  119. Ying Zhang, Robert P. Dick, Krishnendu Chakrabarty
    Energy-aware deterministic fault tolerance in distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:550-555 [Conf]
  120. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta
    Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:556-561 [Conf]
  121. Xiaoping Hu, Radu Marculescu
    Adaptive data partitioning for ambient multimedia. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:562-565 [Conf]
  122. Siddharth Choudhuri, Rabi N. Mahapatra
    Energy characterization of filesystems for diskless embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:566-569 [Conf]
  123. Vidyasagar Nookala, Sachin S. Sapatnekar
    A method for correcting the functionality of a wire-pipelined circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:570-575 [Conf]
  124. Mario R. Casu, Luca Macchiarulo
    A new approach to latency insensitive design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:576-581 [Conf]
  125. Qinghua Liu, Malgorzata Marek-Sadowska
    Pre-layout wire length and congestion estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:582-587 [Conf]
  126. Abhijit Davare, Kelvin Lwin, Alex Kondratyev, Alberto L. Sangiovanni-Vincentelli
    The best of both worlds: the efficient asynchronous implementation of synchronous specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:588-591 [Conf]
  127. Cheoljoo Jeong, Steven M. Nowick
    Fast hazard detection in combinational circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:592-595 [Conf]
  128. Margarida F. Jacome, Chen He, Gustavo de Veciana, Stephen Bijansky
    Defect tolerant probabilistic design paradigm for nanotechnologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:596-601 [Conf]
  129. Jason Cong, Yiping Fan, Zhiru Zhang
    Architecture-level synthesis for automatic interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:602-607 [Conf]
  130. Samar Abdi, Daniel Gajski
    Automatic generation of equivalent architecture model from functional specification. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:608-613 [Conf]
  131. Bo Yang, Ramesh Karri, David A. McGrew
    Divide-and-concatenate: an architecture level optimization technique for universal hash functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:614-617 [Conf]
  132. Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti
    Performance analysis of different arbitration algorithms of the AMBA AHB bus. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:618-621 [Conf]
  133. Tom Korsmeyer, Jun Zeng, Ken Greiner
    Design tools for BioMEMS. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:622-628 [Conf]
  134. Jacob White
    CAD challenges in BioMEMS design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:629-632 [Conf]
  135. Rob A. Rutenbar, Tony Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser
    Will Moore's Law rule in the land of analog? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:633- [Conf]
  136. Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
    Profile-guided microarchitectural floorplanning for deep submicron processor design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:634-639 [Conf]
  137. Changbo Long, Lucanus Simonson, Weiping Liao, Lei He
    Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:640-645 [Conf]
  138. Jing Li, Tan Yan, Bo Yang, Juebang Yu, Chunhui Li
    A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:646-651 [Conf]
  139. Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
    Worst-case circuit delay taking into account power supply variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:652-657 [Conf]
  140. Aseem Agarwal, Florentin Dartu, David Blaauw
    Statistical gate delay model considering multiple input switching. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:658-663 [Conf]
  141. Dongwoo Lee, Vladimir Zolotov, David Blaauw
    Static timing analysis using backward signal propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:664-669 [Conf]
  142. Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam Chu, Donald Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, Steve Dodson
    Design and implementation of the POWER5 microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:670-672 [Conf]
  143. Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, Ana Sonia Leon
    A dual-core 64b ultraSPARC microprocessor for dense server applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:673-677 [Conf]
  144. Daniel J. Deleganes, Micah Barany, George Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal Wijeratne
    Low voltage swing logic circuits for a Pentium 4 processor integer core. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:678-680 [Conf]
  145. Wayne Wolf
    The future of multiprocessor systems-on-chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:681-685 [Conf]
  146. Tim Kogel, Heinrich Meyr
    Heterogeneous MP-SoC: the solution to energy-efficient signal processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:686-691 [Conf]
  147. Chris Rowen, Steve Leibson
    Flexible architectures for engineering successful SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:692-697 [Conf]
  148. Prashant Saxena, Bill Halpin
    Modeling repeaters explicitly within analytical placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:699-704 [Conf]
  149. Bernd Obermeier, Frank M. Johannes
    Quadratic placement using an improved timing model. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:705-710 [Conf]
  150. Milos Hrkic, John Lillis, Giancarlo Beraudo
    An approach to placement-coupled logic replication. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:711-716 [Conf]
  151. Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
    A novel approach for flexible and consistent ADL-driven ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:717-722 [Conf]
  152. Pan Yu, Tulika Mitra
    Characterizing embedded applications for instruction-set extensible processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:723-728 [Conf]
  153. Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt
    Introduction of local memory elements in instruction set extensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:729-734 [Conf]
  154. Fei Li, Yan Lin, Lei He
    FPGA power reduction using configurable dual-Vdd. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:735-740 [Conf]
  155. Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
    Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:741-746 [Conf]
  156. Nobuyuki Ohba, Kohji Takano
    An SoC design methodology using FPGAs and embedded microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:747-752 [Conf]
  157. Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
    Security as a new dimension in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:753-760 [Conf]
  158. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Tradeoffs between date oxide leakage and delay for dual Tox circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:761-766 [Conf]
  159. Kaviraj Chopra, Sarma B. K. Vrudhula
    Implicit pseudo boolean enumeration algorithms for input vector control. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:767-772 [Conf]
  160. Ashish Srivastava, Dennis Sylvester, David Blaauw
    Statistical optimization of leakage power considering process variations using dual-Vth and sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:773-778 [Conf]
  161. Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw
    Leakage-and crosstalk-aware bus encoding for total power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:779-782 [Conf]
  162. Ashish Srivastava, Dennis Sylvester, David Blaauw
    Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:783-787 [Conf]
  163. Shu Yan, Vivek Sarin, Weiping Shi
    Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:788-793 [Conf]
  164. Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala
    A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:794-799 [Conf]
  165. Satrajit Gupta, Lawrence T. Pileggi
    CHIME: coupled hierarchical inductance model evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:800-805 [Conf]
  166. Sharad Kapur, David E. Long
    Large-scale full-wave simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:806-809 [Conf]
  167. Yuichi Tanji, Hideki Asai
    Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:810-813 [Conf]
  168. Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu
    Re-synthesis for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:814-819 [Conf]
  169. Aiqun Cao, Cheng-Kok Koh
    Post-layout logic optimization of domino circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:820-825 [Conf]
  170. Peter Tummeltshammer, James C. Hoe, Markus Püschel
    Multiple constant multiplication by time-multiplexed mapping of addition chains. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:826-829 [Conf]
  171. Hemangee K. Kapoor, Mark B. Josephs
    Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:830-833 [Conf]
  172. Pawel Kerntopf
    A new heuristic algorithm for reversible logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:834-837 [Conf]
  173. William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski
    Quantum logic synthesis by symbolic reachability analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:838-841 [Conf]
  174. Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi
    A frequency relaxation approach for analog/RF system-level simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:842-847 [Conf]
  175. Ting Mei, Jaijeet S. Roychowdhury, Todd S. Coffey, Scott A. Hutchinson, David M. Day
    Robust, stable time-domain methods for solving MPDEs of fast/slow systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:848-853 [Conf]
  176. Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:854-859 [Conf]
  177. Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi
    Hierarchical approach to exact symbolic analysis of large analog circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:860-863 [Conf]
  178. Baolin Yang, Bruce McGaughy
    An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:864-867 [Conf]
  179. Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner
    Theoretical and practical limits of dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:868-873 [Conf]
  180. R. Reed Taylor, Herman Schmit
    Enabling energy efficiency in via-patterned gate array devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:874-878 [Conf]
  181. Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy
    Compact thermal modeling for temperature-aware design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:878-883 [Conf]
  182. Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
    Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:884-887 [Conf]
  183. Rouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum
    Noise characterization of static CMOS gates. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:888-893 [Conf]
  184. Chong Zhao, Xiaoliang Bai, Sujit Dey
    A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:894-899 [Conf]
  185. Li Ding 0002, Pinaki Mazumder
    A novel technique to improve noise immunity of CMOS dynamic logic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:900-903 [Conf]
  186. Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:904-907 [Conf]
  187. Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya
    Debugging HW/SW interface for MPSoC: video encoder system design case study. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:908-913 [Conf]
  188. Srinivasan Murali, Giovanni De Micheli
    SUNMAP: a tool for automatic topology selection and generation for NoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:914-919 [Conf]
  189. Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
    FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:920-923 [Conf]
  190. Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle
    Mapping a domain specific language to a platform FPGA. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:924-927 [Conf]
  191. Irith Pomeranz
    On the generation of scan-based test sets with reachable states for testing under functional operation conditions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:928-933 [Conf]
  192. Peter Wohl, John A. Waicukauski, Sanjay Patel
    Scalable selector architecture for x-tolerant deterministic BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:934-939 [Conf]
  193. Irith Pomeranz
    Scan-BIST based on transition probabilities. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:940-943 [Conf]
  194. Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
    Combining dictionary coding and LFSR reseeding for test data compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:944-947 [Conf]
  195. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual memory window for application-specific reconfigurable coprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:948-953 [Conf]
  196. Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
    Dynamic FPGA routing for just-in-time FPGA compilation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:954-959 [Conf]
  197. Manish Handa, Ranga Vemuri
    An efficient algorithm for finding empty space for online FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:960-965 [Conf]
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