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Conferences in DBLP

Design Automation Conference (DAC) (dac)
1988 (conf/dac/88)

  1. Ian M. Ross
    Future Developments in Information Technology (abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:1- [Conf]
  2. A. Richard Newton
    Twenty-Five Years of Electronic Design Automation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:2- [Conf]
  3. Charles E. Stroud
    An Automated BIST Approach for General Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:3-8 [Conf]
  4. Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha
    Automatic Insertion of BIST Hardware Using VHDL. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:9-15 [Conf]
  5. Catherine H. Gebotys, Mohamed I. Elmasry
    VLSI Design Synthesis with Testability. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:16-21 [Conf]
  6. Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth
    A Defect-Tolerant and Fully Testable PLA. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:22-33 [Conf]
  7. Ramón D. Acosta, Mark Alexandre, Gary Imken, Bill Read
    The Role of VHDL in the MCC CAD System. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:34-39 [Conf]
  8. David R. Coelho
    VHDL: A Call for Standards. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:40-47 [Conf]
  9. Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu
    Verification of VHDL Designs Using VAL. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:48-53 [Conf]
  10. Xinghao Chen, Michael L. Bushnell
    A Module Area Estimator for VLSI Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:54-59 [Conf]
  11. Gerhard Zimmermann
    A New Area and Shape Function Estimation Technique for VLSI Layouts. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:60-65 [Conf]
  12. Shmuel Wimer, Israel Koren, Israel Cederbaum
    Optimal Aspect Ratios of Building Blocks in VLSI. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:66-72 [Conf]
  13. Carl Sechen
    Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:73-80 [Conf]
  14. Barry Whalen
    Automating the Design of Electronic Packaging (tutorial). [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:81- [Conf]
  15. David A. Hodges
    Opportunities in Computer Integrated Manufacturing. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:82-83 [Conf]
  16. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
    Contest: A Concurrent Test Generator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:84-89 [Conf]
  17. C. Thomas Glover, M. Ray Mercer
    A Method of Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:90-95 [Conf]
  18. Wu-Tung Cheng
    Split Circuit Model for Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:96-101 [Conf]
  19. Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder
    A Notation for Describing Multiple Views of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:102-107 [Conf]
  20. Paul J. Drongowski, Jwahar R. Bami, Ranganathan Ramaswamy, Sundar Iyengar, Tsu-Hua Wang
    A Graphical Hardware Design Language. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:108-114 [Conf]
  21. Gotaro Odawara, Masahiro Tomita, Kazuhiko Hattori, Osamu Okuzawa, Toshiaki Hirata, Masayasu Ochiai
    A Human Machine Interface for Silicon Compilation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:115-120 [Conf]
  22. C. P. Ravi Kumar, Sarma Sastry
    Parallel Placement on Reduced Array Architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:121-127 [Conf]
  23. Mehdi R. Zargham
    Parallel Channel Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:128-133 [Conf]
  24. Erik C. Carlson, Rob A. Rutenbar
    Mask Verification on the Connection Machine. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:134-140 [Conf]
  25. Andrew Rappaport
    Future Computing Environments for DA (panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:141- [Conf]
  26. Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni
    On Path Selection in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:142-147 [Conf]
  27. James J. Cherry
    Pearl: A CMOS Timing Analyzer. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:148-153 [Conf]
  28. David E. Wallace, Carlo H. Séquin
    ATV: An Abstract Timing Verifier. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:154-159 [Conf]
  29. Mary L. Bailey, Lawrence Snyder
    An Empirical Study of On-chip Parallelism. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:160-165 [Conf]
  30. Larry Soulé, Tom Blank
    Parallel Logic Simulation on General Purpose Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:166-171 [Conf]
  31. David M. Lewis
    A Programmable Hardware Accelerator for Compiled Electrical Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:172-177 [Conf]
  32. W. Heyns, K. Van Nieuwenhove
    Recursive Channel Router. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:178-182 [Conf]
  33. H. Cai
    Multi-Pads, Single Layer Power Net Routing in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:183-188 [Conf]
  34. Jonathan Rose
    LocusRoute: A Parallel Global Router for Standard Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:189-195 [Conf]
  35. Tom Blank
    Behavioral Modeling for System Design (panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:196- [Conf]
  36. Victoria Stavridou, Howard Barringer, David A. Edwards
    Formal Specification and Verification of Hardware: A Comparative Case Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:197-204 [Conf]
  37. Jean Christophe Madre, Jean-Paul Billon
    Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:205-210 [Conf]
  38. Paliath Narendran, Jonathan Stillman
    Formal Verification of the Sobel Image Processing Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:211-217 [Conf]
  39. Daniel K. Beece, George Deibert, Georgina Papp, Frank Villante
    The IBM Engineering Verification Engine. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:218-224 [Conf]
  40. Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato
    Logic Simulation System Using Simulation Processor (SP). [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:225-230 [Conf]
  41. Yoshiharu Kazama, Yoshiaki Kinoshita, Motonobu Nagafuji, Hiroshi Murayama
    Algorithm for Vectorizing Logic Simulation and Evaluation of "VELVET" Performance. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:231-236 [Conf]
  42. Richard Barth, Bertrand Serlet
    A Structural Representation for VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:237-242 [Conf]
  43. Richard Barth, Bertrand Serlet, Pradeep S. Sindhu
    Parameterized Schematics. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:243-249 [Conf]
  44. Richard Barth, Louis Monier, Bertrand Serlet
    Patchwork: Layout from Schematic Annotations. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:250-255 [Conf]
  45. Wayne Wolf
    What Is a Design Automation Framework, Anyway? (panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:256- [Conf]
  46. Gwo-Dong Chen, Tai-Ming Parng
    A Database Management System for a VLSI Design System. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:257-262 [Conf]
  47. Ying-Kuei Yang
    An Enhanced Data Model for CAD/CAM Database Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:263-268 [Conf]
  48. David Gedye, Randy H. Katz
    Browsing in Chip Design Database. [Citation Graph (1, 0)][DBLP]
    DAC, 1988, pp:269-274 [Conf]
  49. Hong-Tai Chou, Won Kim
    Versions and Change Notification in an Object-Oriented Database System. [Citation Graph (7, 0)][DBLP]
    DAC, 1988, pp:275-281 [Conf]
  50. Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam
    An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:282-287 [Conf]
  51. Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj
    Delay Modeling and Time of Bipolar Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:288-293 [Conf]
  52. Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar
    Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:294-299 [Conf]
  53. Carol V. Gura, Jacob A. Abraham
    Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:300-305 [Conf]
  54. Jimmy Lam, Jean-Marc Delosme
    Performance of a New Annealing Schedule. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:306-311 [Conf]
  55. Sivanarayana Mallela, Lov K. Grover
    Clustering Based Simulated Annealing for Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:312-317 [Conf]
  56. Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
    Proud: A Fast Sea-of-Gates Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:318-323 [Conf]
  57. Lawrence T. Pillage, Ronald A. Rohrer
    A Quadratic Metric with a Simple Solution Scheme for Initial Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:324-329 [Conf]
  58. Michael C. McFarland, Alice C. Parker, Raul Camposano
    Tutorial on High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:330-336 [Conf]
  59. Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn
    The System Architect's Workbench. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:337-343 [Conf]
  60. Denise J. Ecklund, Fred M. Tonge
    A Context Mechanism to Control Sharing in a Design Database. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:344-350 [Conf]
  61. Pieter van der Wolf, T. G. R. van Leuken
    Object Type Oriented Data Modeling for VLSI Data Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:351-356 [Conf]
  62. Ing Widya, T. G. R. van Leuken, Pieter van der Wolf
    Concurrency Control in a VLSI Design Database. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:357-362 [Conf]
  63. Agnieszka Konczykowska, M. Bon
    Automated Design Software for Switched-Capacitor IC's with Symbolic Simulator SCYMBAL. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:363-368 [Conf]
  64. E. Berkcan, Manuel A. d'Abreu, W. Laughton
    Analog Compilation Based on Successive Decompositions. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:369-375 [Conf]
  65. Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen
    Model Development and Verification for High Level Analog Blocks. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:376-382 [Conf]
  66. David G. Boyer
    Symbolic Layout Compaction Review. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:383-389 [Conf]
  67. Werner L. Schiele
    Compaction with Incremental Over-Constraint Resolution. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:390-395 [Conf]
  68. David Marple, Michiel Smulders, Henk Hegen
    An Efficient Compactor for 45° Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:396-402 [Conf]
  69. Nels Vander Zanden, Daniel Gajski
    MILO: A Microarchitecture and Logic Optimizer. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:403-408 [Conf]
  70. Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou
    BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:409-414 [Conf]
  71. Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose
    Bridge: A Versatile Behavioral Synthesis System. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:415-420 [Conf]
  72. Chin-Long Wey, Tsin-Yuan Chang
    PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:421-426 [Conf]
  73. Martin Helliwell, Marek A. Perkowski
    A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:427-432 [Conf]
  74. Wayne Wolf, Kurt Keutzer, Janaki Akella
    A Kernel-Finding State Assignment Algorithm for Multi-Level Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:433-438 [Conf]
  75. Yoichi Shiraishi, Jun'ya Sakemi, Makoto Kutsuwada, Akira Tsukizoe, Takashi Satoh
    A High Packing Density Module Generator for CMOS Logic Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:439-444 [Conf]
  76. Donald G. Baltus, Jonathan Allen
    SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:445-452 [Conf]
  77. Fred W. Obermeier, Randy H. Katz
    An Electrical Optimizer that Considers Physical Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:453-459 [Conf]
  78. Don Stark, Mark Horowitz
    Analyzing CMOS Power Supply Networks Using Ariel. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:460-464 [Conf]
  79. Volker Henkel, Ulrich Golze
    RISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:465-470 [Conf]
  80. Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
    Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:471-475 [Conf]
  81. Randal E. Bryant
    CAD Tool Needs for System Designers. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:476- [Conf]
  82. Gaetano Borriello, Ewald Detjens
    High-Level Synthesis: Current Status and Future Directions. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:477-482 [Conf]
  83. Giovanni De Micheli, David C. Ku
    HERCULES - a System for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:483-488 [Conf]
  84. Raul Camposano
    Design Process Model in the Yorktown Silicon Compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:489-494 [Conf]
  85. Derek L. Beatty, Randal E. Bryant
    Fast Incremental Circuit Analysis Using Extracted Hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:495-500 [Conf]
  86. Kiyoung Choi, Sun Young Hwang, Tom Blank
    Incremental-in-time Algorithm for Digital Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:501-505 [Conf]
  87. Dan Adler
    A Dynamically-Directed Switch Model for MOS Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:506-511 [Conf]
  88. Makoto Takashima, Atsuhiko Ikeuchi, Shoichi Kojima, Toshikazu Tanaka, Tamaki Saitou, Jun-ichi Sakata
    A Circuit Comparison System with Rule-Based Functional Isomorphism Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:512-516 [Conf]
  89. Michael Boehner
    LOGEX - an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:517-522 [Conf]
  90. Alexander C. Papaspyrdis
    A Prolog-Based Connectivity Verification Tool. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:523-527 [Conf]
  91. Alfred E. Dunlop
    Will Cell Generation Displace Standard Cells? [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:528- [Conf]
  92. Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig
    CORAL II: Linking Behavior and Structure in an IC Design System. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:529-535 [Conf]
  93. Barry M. Pangre
    Splicer: A Heuristic Approach to Connectivity Binding. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:536-541 [Conf]
  94. Rajiv Jain, Alice C. Parker, Nohbyung Park
    Module Selection for Pipelined Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:542-547 [Conf]
  95. Rami R. Razouk
    The Use of Petri Nets for Modeling Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:548-553 [Conf]
  96. Y. S. Kuo, T. C. Chern, Wei Kuan Shih
    Fast Algorithm for Optimal Layer Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:554-559 [Conf]
  97. H. Cai
    Connectivity Biased Channel Construction and Ordering for Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:560-565 [Conf]
  98. Xianji Yao, Massaki Yamada, C. L. Liu
    A New Approach to the Pin Assignment Problem. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:566-572 [Conf]
  99. Xiao-Ming Xiong, Ernest S. Kuh
    The Constrained Via Minimization Problem for PCB and VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:573-578 [Conf]
  100. Chien-Hung Chao, F. Gail Gray
    Micro-operation Perturbations in Chip Level Fault Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:579-582 [Conf]
  101. Fredrick J. Hill, Eltayeb Abuelyamen, Wei-Kang Huang, Guo-Qiang Shen
    A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:583-586 [Conf]
  102. Mehmet A. Cirit
    Switch Level Random Pattern Testability Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:587-590 [Conf]
  103. Weiwei Mao, Michael D. Ciletti
    Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:591-596 [Conf]
  104. Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler
    CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:597-600 [Conf]
  105. Dov Harel, Balakrishnan Krishnamurthy
    A Graph Compaction Approach to Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:601-604 [Conf]
  106. Chen-Shang Lin, Hong-Fa Ho
    Automatic Functional Test Program Generation for Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:605-608 [Conf]
  107. Sy-Yen Kuo, W. Kent Fuchs
    Spare Allocation and Reconfiguration in Large Area VLSI. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:609-612 [Conf]
  108. Steve Meyer
    A Data Structure for Circuit Net Lists. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:613-616 [Conf]
  109. Michel Heydemann, Alain Plaignaud, Daniel Dure
    The Architecture of a Highly Integrated Simulation System. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:617-621 [Conf]
  110. William C. Diss
    Circuit Compilers don't have to be Slow. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:622-627 [Conf]
  111. Tai A. Ly, Emil F. Girczyc
    Constraint Propagation in an Object-Oriented IC Design Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:628-633 [Conf]
  112. Sheldon S. L. Chang
    Design Automation for the Component Parts Industry. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:634-637 [Conf]
  113. Marwan A. Jabri
    Automatic Building of Graphs for Rectangular Dualisation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:638-641 [Conf]
  114. Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa
    Automatic Layout Procedures for Serial Routing Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:642-645 [Conf]
  115. Richard I. Hartley, Peter F. Corbett
    A Digit-Serial Silicon Compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:646-649 [Conf]
  116. Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
    DECOMPOSER: A Synthesizer for Systolic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:650-653 [Conf]
  117. Thomas Bergstraesser, Jürgen Gessner, Karlheinz Hafner, Stefan Wallstab
    SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:654-657 [Conf]
  118. Atreyi Chakraverti, Moon-Jung Chung
    Routing Algorithm for Gate Array Macro Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:658-662 [Conf]
  119. Jingsheng Cong, D. F. Wong
    How to Obtain More Compactable Channel Routing Solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:663-666 [Conf]
  120. R. Eric Lunow
    A Channelless, Multilayer Router. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:667-671 [Conf]
  121. Michael H. Arnold, Walter S. Scott
    An Interactive Maze Router with Hints. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:672-676 [Conf]
  122. Chung-Kuan Cheng, David N. Deutsch
    Improved Channel Routing by Via Minimization and Shifting. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:677-680 [Conf]
  123. Inderpal S. Bhandari, Mark Hirsch, Daniel P. Siewiorek
    The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-cut Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:681-685 [Conf]
  124. Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
    Fault Simulation in a Distributed Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:686-691 [Conf]
  125. Silvano Gai, Pier Luca Montessoro, Fabio Somenzi
    The Performance of the Concurrent Fault Simulation Algorithms in MOZART. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:692-697 [Conf]
  126. Akira Motohara, Motohide Murakami, Miki Urano, Yasuo Masuda, Masahide Sugano
    An Approach to Fast Hierarchical Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:698-703 [Conf]
  127. Jacob Savir
    Why Partial Design Verification Works Better Than It Should. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:704-707 [Conf]
  128. Richard H. Lathrop, Robert J. Hall, Gavan Duffy, K. Mark Alexander, Robert S. Kirk
    Advances in Functional Abstraction from Structure. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:708-711 [Conf]
  129. Craig Hansen
    Hardware Logic Simulation by Compilation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:712-716 [Conf]
  130. Yoshio Takamine, Shunsuke Miyamoto, Shigeo Nagashima, Masayuki Miyoshi, Shun Kawabe
    Clock Event Suppression Algorithm of VELVET and Its Application to S-820 Development. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:716-719 [Conf]
  131. H. C. Yen, Subbarao Ghanta, David Hung-Chang Du
    A Path Selection Algorithm for Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:720-723 [Conf]
  132. Steven K. Sherman
    Algorithms for Timing Requirement Analysis and Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:724-727 [Conf]
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