Conferences in DBLP
Marc Tremblay , Guillermo Maturana , Atsushi Inoue , Leslie Kohn A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Yang , David Gao , Jamshid Mostoufi , Raju Joshi , Paul Loewenstein System Design Methodology of UltraSPARC-I. [Citation Graph (0, 0)][DBLP ] Conf ] James Gateley , Miriam Blatt , Dennis Chen , Scott Cooke , Piyush Desai , Manjunath Doreswamy , Mark Elgood , Gary Feierbach , Tim Goldsbury , Dale Greenley , Raju Joshi , Mike Khosraviani , Robert Kwong , Manish Motwani , Chitresh Narasimhaiah , Sam J. Nicolino Jr. , Tooru Ozeki , Gary Peterson , Chris Salzmann , Nasser Shayesteh , Jeffrey Whitman , Pak Wong UltraSPARC-I Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] A. Cao , A. Adalal , J. Bauman , P. Delisle , P. Dedood , P. Donehue , M. Dell'OcaKhouja , T. Doan , Manjunath Doreswamy , P. Ferolito , O. Geva , D. Greenhill , S. Gopaladhine , J. Irwin , L. Lev , J. MacDonald , M. Ma , Samir Mitra , P. Patel , A. Prabhu , R. Puranik , S. Rozanski , N. Ross , P. Saggurti , S. Simovich , R. Sunder , B. Sur , W. Vercruysse , Michelle Wong , P. Yip , Robert K. Yu , J. Zhou , Gregory B. Zyner CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc. [Citation Graph (0, 0)][DBLP ] Conf ] Srilatha Manne , Abelardo Pardo , R. Iris Bahar , Gary D. Hachtel , Fabio Somenzi , Enrico Macii , Massimo Poncino Computing the Maximum Power Cycles of a Sequential Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Jui-Ming Chang , Massoud Pedram Register Allocation and Binding for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Farrahi , Gustavo E. Téllez , Majid Sarrafzadeh Memory Segmentation to Exploit Sleep Mode Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Raul San Martin , John P. Knight Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hua Wang , TingTing Hwang Boolean Matching for Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Wurth , Klaus Eckl , Kurt Antreich Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Stanion , Carl Sechen A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Zen Shen , Juinn-Dar Huang , Shih-Min Chao Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Hirendu Vaishnav , Massoud Pedram Minimizing the Routing Cost During Logic Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen T. Frezza , Steven P. Levitan , Panos K. Chrysanthis Requirements-Based Design Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Eric W. Johnson , Jay B. Brockman Incorporating Design Schedule Management into a Flow Management System. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim Altmeyer , Bernd Schürmann , Martin Schütze Generating ECAD Framework Code from Abstract Models. [Citation Graph (0, 0)][DBLP ] Conf ] Ansgar Bredenfeld , Raul Camposano Tool Integration and Construction Using Generated Graph-Based Design Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Tai Ly , David Knapp , Ron Miller , Don MacMillen Scheduling Using Behavioral Templates. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Mani B. Srivastava Rephasing: A Transformation Technique for the Manipulation of Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Y. G. DeCastelo-Vide-e-Souza , Miodrag Potkonjak , Alice C. Parker Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Sparmann , D. Luxenburger , Kwang-Ting Cheng , Sudhakar M. Reddy Fast Identification of Robust Dependent Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Synthesis-for-Testability of Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman , Ismed Hartanto , W. Kent Fuchs , Elizabeth M. Rudnick , Sreejit Chakravarty , Janak H. Patel Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. [Citation Graph (0, 0)][DBLP ] Conf ] Roger D. Chamberlain Parallel Logic Simulation of VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Walker , Sumit Ghosh Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Robert S. French , Monica S. Lam , Jeremy R. Levitt , Kunle Olukotun A General Method for Compiling Event-Driven Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Kai Cheng , Youn-Long Lin A Transformation-Based Approach for Storage Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Yi Wu , Youn-Long Lin Register Minimization beyond Sharing among Variables. [Citation Graph (0, 0)][DBLP ] Conf ] Elof Frank , Salil Raje , Majid Sarrafzadeh Constrained Register Allocation in Bus Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Aiman H. El-Maleh , Thomas E. Marchok , Janusz Rajski , Wojciech Maly On Test Set Preservation of Retimed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , Janak H. Patel Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , C. L. Liu Partial Scan with Pre-selected Scan Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , So-Zen Yao Spectral Partitioning: The More Eigenvectors, The Better. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Sawkar , Donald E. Thomas Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Lung-Tien Liu , Ming-Ter Kuo , Chung-Kuan Cheng , T. C. Hu Performance-Driven Partitioning Using a Replication Graph Approach. [Citation Graph (0, 0)][DBLP ] Conf ] William Swartz , Carl Sechen Timing Driven Placement for Large Standard Cell Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lars W. Hagen , Dennis J.-H. Huang , Andrew B. Kahng Quantified Suboptimality of VLSI Layout Heuristics. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Albrecht Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zepter , Thorsten Grötker , Heinrich Meyr Digital Receiver Design Using VHDL Generation from Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Charles H. Malley , Max Dieudonné Logic Verification Methodology for PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Sharad Malik A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sasan Iman , Massoud Pedram Logic Extraction and Factorization for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Lavagno , Patrick C. McGeer , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Chandna , C. David Kibler , Richard B. Brown , Mark Roberts , Karem A. Sakallah The Aurora RAM Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Rekhi , J. Donald Trotter , Daniel H. Linder Automatic Layout Synthesis of Leaf Cells. [Citation Graph (0, 0)][DBLP ] Conf ] N. P. van der Meijs , A. J. van Genderen Delayed Frontal Solution for Finite-Element Based Resistance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Aharon Aharon , Dave Goodman , Moshe Levinger , Yossi Lichtenstein , Yossi Malka , Charlotte Metzger , Moshe Molcho , Gil Shurek Test Program Generation for Functional Verification of PowerPC Processors in IBM. [Citation Graph (0, 0)][DBLP ] Conf ] David Knapp , Tai Ly , Don MacMillen , Ron Miller Behavioral Synthesis Methodology for HDL-Based Specification and Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Bombana , Patrizia Cavalloro , Salvatore Conigliaro , Roger B. Hughes , Gerry Musgrave , Giuseppe Zaza Design-Flow and Synthesis for ASICs: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Bormann , Jörg Lohse , Michael Payer , Gerd Venzl Model Checking in Industrial Hardware Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar N. Lalgudi , Marios C. Papaefthymiou DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul B. Deokar , Sachin S. Sapatnekar A Fresh Look at Retiming Via Clock Skew Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Vigyan Singhal , Carl Pixley , Richard L. Rudell , Robert K. Brayton The Validity of Retiming Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ireneusz Karkowski , Ralph H. J. M. Otten Retiming Synchronous Circuitry with Imprecise Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Shihming Liu , Massoud Pedram , Alvin M. Despain A Fast State Assignment Procedure for Large FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Kassab , Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer Software Accelerated Functional Fault Simulation for Data-Path Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Krieger , Bernd Becker , Martin Keim Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Haluk Konuk , F. Joel Ferguson , Tracy Larrabee Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. [Citation Graph (0, 0)][DBLP ] Conf ] Lluis Ribas , Jordi Carrabina Analysis of Switch-Level Faults by Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Krauter , Rohini Gupta , John Willis , Lawrence T. Pileggi Transmission Line Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Gupta , Byron Krauter , Bogdan Tutuianu , John Willis , Lawrence T. Pileggi The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Vasant B. Rao Delay Analysis of the Distributed RC Line. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Miguel Silveira , Mattan Kamon , Jacob White Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Mehrotra , Paul D. Franzon , Michael Steer Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Chuck Monahan , Forrest Brewer Symbolic Modeling and Evaluation of Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Donald S. Gelosh , Dorothy E. Setliff Deriving Efficient Area and Delay Estimates by Modeling Layout Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Bern , Christoph Meinel , Anna Slobodová Efficient OBDD-Based Boolean Manipulation in CAD beyond Current Limits. [Citation Graph (0, 0)][DBLP ] Conf ] Subodh M. Reddy , Wolfgang Kunz , Dhiraj K. Pradhan Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jawahar Jain , Rajarshi Mukherjee , Masahiro Fujita Advanced Verification Techniques Based on Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Orna Grumberg , Kenneth L. McMillan , Xudong Zhao Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Wim Kruiskamp , Domine Leenaerts DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan L. Wemple , Andrew T. Yang Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] Koen Lampaert , Georges G. E. Gielen , Willy M. C. Sansen Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bapiraju Vinnakota , Ramesh Harjani , Nicholas J. Stessman System-Level Design for Test of Fully Differential Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yau-Tsun Steven Li , Sharad Malik Performance Analysis of Embedded Software Using Implicit Path Enumeration. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Gaetano Borriello Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjiv Narayan , Daniel Gajski Interfacing Incompatible Protocols Using Interface Process Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , Roland W. Freund Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Telichevesky , Kenneth S. Kundert , Jacob White Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Chou , Tom Korsmeyer , Jacob White Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Joe G. Xi , Wayne Wei-Ming Dai Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Vittal , Malgorzata Marek-Sadowska Power Optimal Buffered Clock Tree Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Vittal , Malgorzata Marek-Sadowska Power Distribution Topology Design. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis J.-H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao On the Bounded-Skew Clock and Steiner Routing Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Asim Smailagic , Daniel P. Siewiorek , Drew Anderson , Chris Kasabach , Thomas L. Martin , John Stivoric Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Mancini , Dave Yurach , Spiros Boucouris A Methodology for HW-SW Codesign in ATM. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Silburt , Ian Perryman , Janick Bergeron , Stacy Nichols , Mario Dufresne , Greg Ward Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant , Yirng-An Chen Verification of Arithmetic Circuits with Binary Moment Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Kimura Residue BDD and Its Application to the Verification of Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zheng Zhou , Wayne Burleson Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Kei Mak , D. F. Wong On Optimal Board-Level Routing for FPGA-Based Logic Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuh-Sheng Lee , Allen C.-H. Wu A Performance and Routability Driven Router for FPGAs Considering Path Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Alexander , Gabriel Robins New Performance-Driven FPGA Routing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Liang Wu , Malgorzata Marek-Sadowska Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Trimberger Effects of FPGA Architecture on FPGA Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Mário J. Silva , Randy H. Katz The Case for Design Using the World Wide Web. [Citation Graph (0, 0)][DBLP ] Conf ] Massimiliano Chiodo , Paolo Giusto , Attila Jurecska , Luciano Lavagno , Harry Hsieh , Kei Suzuki , Alberto L. Sangiovanni-Vincentelli , Ellen Sentovich Synthesis of Software Programs for Embedded Control Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Adwin H. Timmer , Marino T. J. Strik , Jef L. van Meerbergen , Jochen A. G. Jess Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Stan Y. Liao , Srinivas Devadas , Kurt Keutzer , Steven W. K. Tjiang , Albert Wang Code Optimization Techniques for Embedded DSP Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Bieker , Peter Marwedel Retargetable Self-Test Program Generation Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Huzefa Mehta , Manjit Borah , Robert Michael Owens , Mary Jane Irwin Accurate Estimation of Combinational Circuit Activity. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm , Michael Y. Zhang Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Marculescu , Diana Marculescu , Massoud Pedram Efficient Power Estimation for Highly Correlated Input Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm , Shashank Goel , Ibrahim N. Hajj Power Estimation in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Jean Christophe Madre New Ideas for Solving Covering Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Chang Lin , Kuang-Chien Chen , Shih-Chieh Chang , Malgorzata Marek-Sadowska , Kwang-Ting Cheng Logic Synthesis for Engineering Change. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichi Nakamura , Takeshi Yoshimura A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Yuguchi , Yuichi Nakamura , Kazutoshi Wakabayashi , Tomoyuki Fujita Multi-Level Logic Minimization Based on Multi-Signal Implications. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , Malgorzata Marek-Sadowska , Kwang-Ting Cheng An Efficient Algorithm for Local Don't Care Sets Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Rohfleisch , Bernd Wurth , Kurt Antreich Logic Clause Analysis for Delay Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? [Citation Graph (0, 0)][DBLP ] Conf ] Cristian A. Giumale , Hilary J. Kahn Information Models of VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Neal S. Stollon , John D. Provence Measures of Syntactic Complexity for Modeling Behavioral VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Menezes , Satyamurthy Pullela , Lawrence T. Pileggi Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-fuw Lee , Donald T. Tang An Algorithm for Incremental Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Dal Fabbro , Bruno Franzini , Luigi Croce , Carlo Guardiani An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Jain , Randal E. Bryant , Alok Jain Automatic Clock Abstraction from Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Gjalt G. de Jong , Tilman Kolks Hierarchical Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Milton H. Sawasaki , Chantal Ykman-Couvreur , Bill Lin Externally Hazard-Free Implementations of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Vanbekbergen , Albert Wang , Kurt Keutzer A Design and Validation System for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 