Conferences in DBLP
Rodney Phelps , Michael Krasnicki , Rob A. Rutenbar , L. Richard Carley , James R. Hellums A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Vancorenland , Carl De Ranter , Michiel Steyaert , Georges G. E. Gielen Optimal RF design using smart evolutionary algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Carl De Ranter , B. De Muer , Geert Van der Plas , Peter J. Vancorenland , Michiel Steyaert , Georges G. E. Gielen , Willy M. C. Sansen CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Guardiani , Sharad Saxena , Patrick McNamara , Phillip Schumaker , Dale Coder An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Pi , C.-J. Richard Shi Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] In-Ho Moon , James H. Kukula , Kavita Ravi , Fabio Somenzi To split or to conjoin: the question in image computation. [Citation Graph (0, 0)][DBLP ] Conf ] Roderick Bloem , Kavita Ravi , Fabio Somenzi Symbolic guided search for CTL model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Yang , Andreas Tiemeyer Lazy symbolic model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Hett , Christoph Scholl , Bernd Becker Distance driven finite state machine traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Masahiro Fujita Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Ian G. Harris , Russell Tessier Interconnect testing in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Alex Orailoglu Improved fault diagnosis in scan-based BIST via superposition. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On diagnosis of pattern-dependent delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw On-chip inductance modeling and analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Eileen You , Lakshminarasimh Varadadesikan , John MacDonald , Wieze Xie A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] H. Levy , W. Scott , Don MacMillen , Jacob White A rank-one update method for efficient processing of interconnect parasitics in timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sudhakar Muddu , Egino Sarto On switch factor based analysis of coupled RC interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , Cheming Hu , Mark Horowitz , Stephen Y. Chow Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Dirk-Jan Jongeneel , Yosinori Watanabe , Robert K. Brayton , Ralph H. J. M. Otten Area and search space control for technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Congguang Yang , Maciej J. Ciesielski , Vigyan Singhal BDS: a BDD-based logic optimization system. [Citation Graph (0, 0)][DBLP ] Conf ] Junhyung Um , Taewhan Kim , C. L. Liu A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , D. F. Wong Optimal low power X OR gate decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Seapahn Meguerdichian , Miodrag Potkonjak Watermarking while preserving the critical path. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev , Randal E. Bryant Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Yang Huang , Kwang-Ting Cheng Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Wilson , David L. Dill Reliable verification using symbolic simulation with scalar values. [Citation Graph (0, 0)][DBLP ] Conf ] David W. Currie , Alan J. Hu , Sreeranga P. Rajan Automatic formal verification of DSP software. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian , Erik Jan Marinissen System chip test: how will it impact your design? [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Sujit Dey , Mike Rodgers , Kaushik Roy Test challenges for deep sub-micron technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Min Zhao , Rajendran Panda , Sachin S. Sapatnekar , Tim Edwards , Rajat Chaudhry , David Blaauw Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP ] Conf ] Sani R. Nassif , Joseph N. Kozhaya Fast power grid simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Rajat Chaudhry , David Blaauw , Rajendran Panda , Tim Edwards Current signature compression for IR-drop analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas Impact of interconnect variations on the clock skew of a gigahertz microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Vikas Mehrotra , Shiou Lin Sam , Duane S. Boning , Anantha Chandrakasan , Rakesh Vallishayee , Sani R. Nassif A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano , Jacob Greidinger , Patrick Groeneveld , Michael Jackson , Lawrence T. Pileggi , Louis Scheffer Design closure (panel session): hope or hype? [Citation Graph (0, 0)][DBLP ] Conf ] Baolin Yang , Joel R. Phillips A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Joel R. Phillips Projection frameworks for model reduction of weakly nonlinear systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli V. Kashyap , Byron Krauter A realizable driving point model for on-chip interconnect with inductance. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Goel , William R. Lee Formal verification of an IBM CoreConnect processor local bus arbiter core. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Aagaard , Robert B. Jones , Roope Kaivola , Katherine R. Kohatsu , Carl-Johan H. Seger Formal verification of iterative algorithms in microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Efficient error detection, localization, and correction for FPGA-based debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Shukri J. Souri , Kaustav Banerjee , Amit Mehrotra , Krishna Saraswat Multiple Si layer ICs: motivation, performance analysis, and design implications. [Citation Graph (0, 0)][DBLP ] Conf ] V. E. Boros , Aleksandar D. Rakic , Sri Parameswaran High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. [Citation Graph (0, 0)][DBLP ] Conf ] Michael T. Niemier , Michael J. Kontz , Peter M. Kogge A design of and design tools for a novel quantum dot based microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Rafi Levy , David Blaauw , Gabi Braca , Aurobindo Dasgupta , Amir Grinshpon , Chanhee Oh , Boaz Orshav , Supamas Sirichotiyakul , Vladimir Zolotov ClariNet: a noise analysis tool for deep submicron design. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard , Dae-Jin Kim Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Somasekhar , Seung Hoon Choi , Kaushik Roy , Yibin Ye , Vivek De Dynamic noise analysis in precharge-evaluate circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Janet Meiling Wang , Tuyen V. Nguyen Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer Smith , Tom Quan , Andrew B. Kahng EDA meets.COM (panel session): how E-services will change the EDA business model. [Citation Graph (0, 0)][DBLP ] Conf ] Clayton B. McDonald , Randal E. Bryant Symbolic timing simulation using cluster scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Soha Hassoun Critical path analysis using a dynamically bounded delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi TACO: timing analysis with coupling. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Rajendran Panda , Abhijit Das Removing user specified false paths from timing graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Sung Kyu Lim , Chang Wu Performance driven multi-level and multiway partitioning with retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Wook Kim , Unni Narayanan , Sung-Mo Kang Domino logic synthesis minimizing crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wei Jim Chang , Chung-Kuan Cheng , Peter Suaris , Malgorzata Marek-Sadowska Fast post-placement rewiring using easily detectable functional symmetries. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Hui Huang Depth optimal incremental mapping for field programmable gate arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Jörg Henkel , Wayne Wolf Code compression for low power embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino Synthesis of application-specific memories for power optimization in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin , Wu Ye Influence of compiler optimizations on system power. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys , Robert J. Gebotys , S. Wiratunga Power minimization derived from architectural-usage of VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Dick , Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha Power analysis of embedded operating systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau Memory aware compilation through accurate timing extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Edwards Compiling Esterel into sequential code. [Citation Graph (0, 0)][DBLP ] Conf ] Thierry J.-F. Omnés , Thierry Franzetti , Francky Catthoor Interactive co-design of high throughput embedded multimedia. [Citation Graph (0, 0)][DBLP ] Conf ] Naji Ghazal , A. Richard Newton , Jan M. Rabaey Predicting performance potential of modern DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Brain Dipert , Danesh Tavana , Barry K. Britton , Bill Harris , Bob Boderson , Chris Rowen Future systems-on-chip: software of hardware design? (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] A. Richard Newton , Walden C. Rhines , Sünke Mehrgardt , Henry Samueli , Tudor Brown Embedded systems design in the new millennium (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] Wu Ye , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin The design and use of simplepower: a cycle-accurate energy estimation tool. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Brandolese , William Fornaciari , Fabio Salice , Donatella Sciuto An instruction-level functionally-based energy estimation model for 32-bits microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Qinru Qiu , Qing Wu , Massoud Pedram Dynamic power management of complex systems using generalized stochastic Petri nets. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Macchiarulo , Malgorzata Marek-Sadowska Wave-steering one-hot encoded FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli Performance analysis and optimization of latency insensitive systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Jagannathan , Sung-Woo Hur , John Lillis A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Minghorng Lai , D. F. Wong Maze routing with buffer insertion and wiresizing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Xin Yuan Routing tree construction under fixed buffer locations. [Citation Graph (0, 0)][DBLP ] Conf ] Thorsten Adler , Hiltrud Brocke , Lars Hedrich , Erich Barke A current driven routing and verification methodology for analog applications. [Citation Graph (0, 0)][DBLP ] Conf ] JoAnn M. Paul , Simon N. Peffers , Donald E. Thomas A codesign virtual machine for hierarchical, balanced hardware/software system modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Desmet , Diederik Verkest , Hugo De Man Operating system based software generation for systems-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Erwin A. de Kock , W. J. M. Smits , Pieter van der Wolf , Jean-Yves Brunel , W. M. Kruijtzer , Paul Lieverse , Kees A. Vissers , Gerben Essink YAPI: application modeling for signal processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Yves Brunel , W. M. Kruijtzer , H. J. H. N. Kenter , Frédéric Pétrot , L. Pasquier , Erwin A. de Kock , W. J. M. Smits COSY communication IP's. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Gaetano Borriello Synthesis and optimization of coordination controllers for distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Derek Chiou , Prabhat Jain , Larry Rudolph , Srinivas Devadas Application-specific memory management for embedded systems using software-controlled caches. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , William R. Lee Designing systems-on-chip using cores. [Citation Graph (0, 0)][DBLP ] Conf ] Marinés Puig-Medina , Gülbin Ezer , Pavlos Konas Verification of configurable processor cores. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty Design of system-on-a-chip test access architectures under place-and-route and power constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Goering , Clifford E. Cummings , Steven E. Schulz , Simon Davidman , John Sanguinetti , Joachim Kunkel , Oz Levia The future of system design languages (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] Gerd Vandersteen , Piet Wambacq , Yves Rolain , Petr Dobrovolný , Stéphane Donnay , Marc Engels , Ivo Bolsens A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Marc van Heijningen , Mustafa Badaroglu , Stéphane Donnay , Marc Engels , Ivo Bolsens High-level simulation of substrate noise generation including power supply noise coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Geert Van der Plas , Jan Vandenbussche , Walter Daems , Antal van den Bosch , Georges G. E. Gielen , Willy M. C. Sansen Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu B*-Trees: a new representation for non-slicing floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Yingxin Pang , Florin Balasa , Koen Lampaert , Chung-Kuan Cheng Block placement with symmetry constraints based on the O-tree non-slicing representation. [Citation Graph (0, 0)][DBLP ] Conf ] Pinghong Chen , Ernest S. Kuh Floorplan sizing by linear programming approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Lian T. Ou , Massoud Pedram Timing-driven placement based on partitioning with dynamic cut-net control. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov Can recursive bisection alone produce routable placements? [Citation Graph (0, 0)][DBLP ] Conf ] Marco Di Natale , Alberto L. Sangiovanni-Vincentelli , Felice Balarin Task scheduling with RT constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Alex Kondratyev , Luciano Lavagno , Marc Massot , Sandra Moral , Claudio Passerone , Yosinori Watanabe , Alberto L. Sangiovanni-Vincentelli Task generation and compile-time scheduling for mixed data-control embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Daehong Kim , Kiyoung Choi Schedulability-driven performance analysis of multiple mode embedded real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Athanassios Boulis , Mani B. Srivastava System design of active basestations based on dynamically reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Yanbing Li , Tim Callahan , Ervan Darnell , Randolph E. Harr , Uday Kurkure , Jon Stockwood Hardware-software co-design of embedded reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kanishka Lahiri , Anand Raghunathan , Ganesh Lakshminarayana , Sujit Dey Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Malik , D. K. Arvind , Edward Lee , Phil Koopman , Alberto L. Sangiovanni-Vincentelli , Wayne Wolf Embedded systems education (panel abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Qingjian Yu , Janet Meiling Wang , Ernest S. Kuh Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. [Citation Graph (0, 0)][DBLP ] Conf ] Emad Gad , Anestis Dounavis , Michel S. Nakhla , Ramachandra Achar Passive model order reduction of multiport distributed interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard N. Sheehan Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments. [Citation Graph (0, 0)][DBLP ] Conf ] Jinsong Zhao Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong Wang , Michael Kirkpatrick , Edwin Hsing-Mean Sha Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications. [Citation Graph (0, 0)][DBLP ] Conf ] M. Narasimhan , J. Ramanujam On lower bounds for scheduling problems in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Horstmannshoff , Heinrich Meyr Efficient building block based RTL code generation from synchronous data flow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Peeter Ellervee , Miguel Miranda , Francky Catthoor , Ahmed Hemani System-level data format exploration for dynamically allocated data structures. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Foty , David Binkley MOSFET modeling and circuit design: re-establishing a lost connection (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Brad L. Hutchings , Brent E. Nelson Using general-purpose programming languages for FPGA design. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Wen Chang , Yu-Tsang Chang An architecture-driven metric for simultaneous placement and global routing for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hartej Singh , Guangming Lu , Eliseu M. Chaves Filho , Rafael Maestre , Ming-Hau Lee , Fadi J. Kurdahi , Nader Bagherzadeh MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Ohr , Rob A. Rutenbar , Henry Chang , Georges G. E. Gielen , Rudolf Koch , Roy McGuffin , K. C. Murphy Survival strategies for mixed-signal systems-on-chip (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , David T. Liu , Jennifer L. Wong , Miodrag Potkonjak Forensic engineering techniques for VLSI CAD tools. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Miodrag Potkonjak Fingerprinting intellectual property using constraint-addition. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Dalpasso , Alessandro Bogliolo , Luca Benini Hardware/software IP protection. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Fin , Franco Fummi A Web-CAD methodology for IP-core analysis and simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Stefano Quer , Fabio Somenzi Optimizing sequential verification by retiming transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Hsieh , Felice Balarin , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Efficient methods for embedded system design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , Joan Carletta , Christos A. Papachristou Synthesis-for-testability of controller-datapath pairs that use gated clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoliang Bai , Sujit Dey , Janusz Rajski Self-test methodology for at-speed test of crosstalk in chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Li Chen , Sujit Dey , Pablo Sanchez , Krishna Sekar , Ying Cheng Embedded hardware and software self-testing methodologies for processor cores. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Attarha , Mehrdad Nourani , Carco Lucas Modeling and simulation of real defects using fuzzy logic. [Citation Graph (0, 0)][DBLP ] Conf ] David G. Chinnery , Kurt Keutzer Closing the gap between ASIC and custom: an ASIC perspective. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Dally , Andrew Chang The role of custom design in ASIC Chips. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Cohn , Rob A. Rutenbar , Steve Young , Chris Malachowsky , Luis Aldaz Case studies: Chip design on the bleeding edge (panel session abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi MINFLOTRANSIT: min-cost flow based transistor sizing tool. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Ketkar , Kishore Kasamsetty , Sachin S. Sapatnekar Convex delay models for transistor sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Mahadevamurty Nemani , Vivek Tiwari Macro-driven circuit design methodology for high-performance datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiqi Tian , D. F. Wong , Robert Boone Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Chen , Andrew B. Kahng , Gabriel Robins , Alexander Zelikovsky Practical iterated fill synthesis for CMP uniformity. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva , Karem A. Sakallah Boolean satisfiability in electronic design automation. [Citation Graph (0, 0)][DBLP ] Conf ] Jawahar Jain , K. Mohanram , Dinos Moundanos , Ingo Wegener , Yuan Lu Analysis of composition complexity and how to obtain smaller canonical graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Lu , Jawahar Jain , Edmund M. Clarke , Masahiro Fujita Efficient variable ordering using aBDD based sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew E. Caldwell , Yu Cao , Andrew B. Kahng , Farinaz Koushanfar , Hua Lu , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester GTX: the MARCO GSRC technology extrapolation system. [Citation Graph (0, 0)][DBLP ] Conf ] Peter van den Hamer , W. P. M. van der Linden , Peter Bingley , N. W. Schellingerhout A system simulation framework. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Fenstermaker , David George , Andrew B. Kahng , Stefanus Mantik , Bart Thielges METRICS: a system architecture for design process optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Igor L. Markov , Christoph Meinel , Ellen Sentovich Web-based frameworks to enable CAD RD (abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Stephen D. Posluszny , N. Aoki , D. Boerstler , P. Coulman , Sang H. Dhong , Brian K. Flachs , H. Peter Hofstee , N. Kojima , Ohsang Kwon , K. Lee , D. Meltzer , Kevin J. Nowka , J. Park , J. Peter , Joel Silberman , Osamu Takahashi , Paul Villarrubia "Timing closure by design, " a high frequency microprocessor design methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Jen-Tien Yen , Qichao Richard Yin Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Cindy Eisner , Irit Shitsevalov , Russ Hoover , Wayne G. Nation , Kyle L. Nelson , Ken Valk A methodology for formal design of hardware control with application to cache coherence protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Drake , Todd D. Basso , Spencer M. Gold , Keith L. Kraver , Phiroze N. Parakh , Claude R. Gauthier , P. Sean Stetson , Richard B. Brown CGaAs PowerPC FXU. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Andrzej J. Strojwas , Sani R. Nassif , Ray Hokinson , Tak Young , Wonjae L. Kang , David Overhauser , Sung-Mo Kang When bad things happen to good chips (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] Joe Kanapka , Joel R. Phillips , Jacob White Fast methods for extraction and sparsification of substrate coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Kapur , David E. Long Large-scale capacitance calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Han Tsai , Sung-Mo Kang Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction. [Citation Graph (0, 0)][DBLP ] Conf ] William E. Dougherty , Donald E. Thomas Unifying behavioral synthesis and physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Hisaaki Katagiri , Keiichi Yasumoto , Akira Kitajima , Teruo Higashino , Kenichi Taniguchi Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization. [Citation Graph (0, 0)][DBLP ] Conf ] Zhan Yu , Kei-Yong Khoo , Alan N. Willson Jr. The use of carry-save representation in joint module selection and retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled Saab , Naim Ben Hamida , Bozena Kaminska Closing the gap between analog and digital. [Citation Graph (0, 0)][DBLP ] Conf ] Venkatram Krishnaswamy , Jeremy Casas , Thomas Tetzlaff A switch level fault simulation environment. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar N. Dwarakanath , Ronald D. Blanton Universal fault simulation using fault tuples. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit T. Zachariah , Sreejit Chakravarty , Carl D. Roth A novel algorithm to extract two-node bridges. [Citation Graph (0, 0)][DBLP ] Conf ] M. Srikanth Rao , S. K. Nandy Power minimization using control generated clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Naehyuck Chang , Kwanho Kim , Jinsung Cho Bus encoding for low-power high-performance memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Seongsoo Lee , Takayasu Sakurai Run-time voltage hopping for low-power real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Naoyuki Kawabe , Kimiyoshi Usami , Miodrag Potkonjak Function-level power estimation methodology for microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Schweikert , Joseph B. Costello , Rajeev Madhavan , Y. C. Pati , Judy Owen , Steve Carlson , Moshe Gavrielov Emerging companies - acquiring minds want to know (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] 