Conferences in DBLP
Mattan Kamon , Steve S. Majors Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Janardhan H. Satyanarayana , Keshab K. Parhi HEAT: Hierarchical Energy Analysis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wolfe Opportunities and Obstacles in Low-Power System-Level CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Sasan Iman , Massoud Pedram POSE: Power Optimization and Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] David Lidsky , Jan M. Rabaey Early Power Exploration - A World Wide Web Application. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ehat Ercanli , Christos A. Papachristou A Register File and Scheduling Model for Application Specific Processor Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , G. Venkatesh , Sunil D. Sherlekar Optimized Code Generation of Multiplication-free Linear Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Chuck Monahan , Forrest Brewer Concurrent Analysis Techniques for Data Path Timing Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Li , Rajesh K. Gupta HDL Optimization Using Timed Decision Tables. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Verlind , Gjalt G. de Jong , Bill Lin Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alexei L. Semenov , Alexandre Yakovlev Verification of asynchronous circuits using Time Petri Net unfolding. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Alexandre Yakovlev Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhakar Kudva , Ganesh Gopalakrishnan , Hans M. Jacobson A Technique for Synthesizing Distributed Burst-mode Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Theobald , Steven M. Nowick , Tao Wu Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhakar Kudva , Ganesh Gopalakrishnan , Hans M. Jacobson , Steven M. Nowick Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. [Citation Graph (0, 0)][DBLP ] Conf ] Frank M. Johannes Partitioning of VLSI Circuits and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jianmin Li , John Lillis , Lung-Tien Liu , Chung-Kuan Cheng New Spectral Linear Placement and Clustering Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Michael D. Hutton , Jerry P. Grossman , Jonathan Rose , Derek G. Corneil Characterization and Parameterized Random Generation of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Dutt , Wenyong Deng A Probability-Based Approach to VLSI Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli , Patrick C. McGeer , Alexander Saldanha Verification of Electronic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Anantha Chandrakasan , Isabel Yang , Carlin Vieri , Dimitri Antoniadis Design Considerations and Tools for Low-voltage Digital System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Wunder , Gunther Lehmann , Klaus D. Müller-Glaser VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Madhav P. Desai , Yao-Tsung Yen A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Wagner , Sujit Dey High-Level Synthesis for Testability: A Survey and Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Iyer , Ramesh Karri Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer Lower Bounds on Test Resources for Scheduled Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio R. W. Todesco , Teresa H. Y. Meng Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Dahlgren Oscillation Control in Logic Simulation using Dynamic Dominance Grahps. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kuang-Chien Chen , Kwang-Ting Cheng , Tien-Chien Lee Compact Vector Generation for Accurate Power Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Ying Tsui , Radu Marculescu , Diana Marculescu , Massoud Pedram Improving the Efficiency of Power Simulators by Input Vector Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Idalina Videira , Paulo Veríssimo , Helena Sarmento Efficient Communication in a Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Sutton , Stephen W. Director A Description Language for Design Process Management. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Hagerman , Stephen W. Director Improved Tool and Data Selection in Task Management. [Citation Graph (0, 0)][DBLP ] Conf ] Eric W. Johnson , Luis A. Castillo , Jay B. Brockman Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process. [Citation Graph (0, 0)][DBLP ] Conf ] Richard L. Rudell Tutorial: Design of a Logic Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert On Solving Covering Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Sungju Park A New Complete Diagnosis Patterns for Wiring Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Ang Chen , Sandeep K. Gupta A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Static Compaction of Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent Basaran , Rob A. Rutenbar An O(n) Algorithm for Transistor Stacking with Performance Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Miliozzi , Iasson Vassiliou , Edoardo Charbon , Enrico Malavasi , Alberto L. Sangiovanni-Vincentelli Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Sawant , Paul Giordano RTL Emulation: The Next Leap in System Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Borchers , Lars Hedrich , Erich Barke Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Chung Tsai , Malgorzata Marek-Sadowska Multilevel Logic Synthesis for Arithmetic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffery P. Hansen , Masatoshi Sekine Synthesis by Spectral Translation Using Boolean Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Shashidhar Thakur , D. F. Wong , Shankar Krishnamoorthy Delay Minimal Decomposition of Multiplexers in Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kuang-Chien Chen , Kwang-Ting Cheng Error Correction Based on Verification Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Chau-Shen Chen , Kuang-Hui Lin , TingTing Hwang Layout Driven Selecting and Chaining of Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Chang Lin , Malgorzata Marek-Sadowska , Kwang-Ting Cheng , Mike Tien-Chien Lee Test Point Insertion: Scan Paths through Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Huoy-Yu Liou , Ting-Ting Y. Lin , Chung-Kuan Cheng Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin J. Kerns , Andrew T. Yang Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury , Robert C. Melville Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Telichevesky , Kenneth S. Kundert , Jacob White Efficient AC and Noise Analysis of Two-Tone RF Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] L. Richard Carley , Georges G. E. Gielen , Rob A. Rutenbar , Willy M. C. Sansen Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Anoosh Hosseini , Dimitrios Mavroidis , Pavlos Konas Code Generation and Analysis for the Functional Verification of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Val Popescu , Bill McNamara Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Gopi Ganapathy , Ram Narayan , Glenn Jorden , Denzil Fernandez , Ming Wang , Jim Nishimura Hardware Emulation for Functional Verification of K5. [Citation Graph (0, 0)][DBLP ] Conf ] James Monaco , David Holloway , Rajesh Raina Functional Verification Methodology for the PowerPC 604 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kantrowitz , Lisa M. Noack I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Sujit Dey , Niraj K. Jha Glitch Analysis and Reduction in Register Transfer Level. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , Mark Spining , Mehrdad Nourani An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Mani B. Srivastava , Miodrag Potkonjak Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] José Monteiro , Srinivas Devadas , Pranav Ashar , Ashutosh Mauskar Scheduling Techniques to Enable Power Management. [Citation Graph (0, 0)][DBLP ] Conf ] Aurobindo Dasgupta , Ramesh Karri Electromigration Reliability Enhancement via Bus Activity Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Krauter , Yu Xia , E. Aykut Dengi , Lawrence T. Pileggi A Sparse Image Method for BEM Capacitance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Narayan R. Aluru , V. B. Nadkarni , James White A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Tausch , Jacob K. White Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios. [Citation Graph (0, 0)][DBLP ] Conf ] Weikai Sun , Wayne Wei-Ming Dai , Wei Hong II Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance. [Citation Graph (0, 0)][DBLP ] Conf ] Joel R. Philips , Eli Chiprout , David D. Ling Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Joe G. Xi , Wayne Wei-Ming Dai Useful-Skew Clock Routing With Gate Sizing for Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Madhav P. Desai , Radenko Cvijetic , James Jensen Sizing of Clock Distribution Networks for High Performance CPU Chips. [Citation Graph (0, 0)][DBLP ] Conf ] John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin , Chin-Yen Ho New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Oh , Iksoo Pyo , Massoud Pedram Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ping Chen , Yao-Wen Chang , D. F. Wong Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Hutchins , Shankar Hemmady How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together. [Citation Graph (0, 0)][DBLP ] Conf ] K. D. Jones , J. P. Privitera The Automatic Generation of Functional Test Vectors for Rambus Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Françoise Casaubieilh , Anthony McIsaac , Mike Benjamin , Mike Bartley , François Pogodalla , Frédéric Rocheteau , Mohamed Belhadj , Jeremy Eggleton , Gérard Mas , Geoff Barrett , Christian Berthet Functional Verification Methodology of Chameleon Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Dean Brown , Naraig Manjikian , Zvonko G. Vranesic , S. Caranci , A. Grbic , R. Grindley , M. Gusat , K. Loveless , Zeljko Zilic , Sinisa Srbljic Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Luca Benini , Bruno Riccò Power Estimation of Cell-Based CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David Ihsin Cheng , Kwang-Ting Cheng , Deborah C. Wang , Malgorzata Marek-Sadowska A New Hybrid Methodology for Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Je Lim , Kyung-Im Son , Heung-Joon Park , Mani Soma A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil P. Khatri , Amit Narayan , Sriram C. Krishnan , Kenneth L. McMillan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Engineering Change in a Non-Deterministic FSM Setting. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh A. Iyer , David E. Long , Miron Abramovici Identifying Sequential Redundancies Without Search. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Higuchi , Yusuke Matsunaga A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Ferrandi , Franco Fummi , Enrico Macii , Massimo Poncino , Donatella Sciuto Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Koch Module Compaction in FPGA-based Regular Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Ter Kuo , Lung-Tien Liu , Chung-Kuan Cheng Network Partitioning into Tree Hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] Danny Z. Chen , Xiaobo Hu Efficient Approximation Algorithms for Floorplan Area Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ping Chen , Yao-Ping Chen , D. F. Wong Optimal Wire-Sizing Formular Under the Elmore Delay Model. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Fujimoto , Takashi Kambe VLSI Design and System Level Verification for the Mini-Disc. [Citation Graph (0, 0)][DBLP ] Conf ] Hisakazu Edamatsu , Satoshi Ikawa , Katsuya Hasegawa Design Methodologies for consumer-use video signal processing LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Miyahara , Yoshimoto Oumi , Seijiro Moriyama Design Methodology for Analog High Frequency ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Murray , Uwe B. Meding , Bill Berg , Yatin Trivedi , Bill McCaffrey , Ted Vucurevich Issues and Answers in CAD Tool Interoperability. [Citation Graph (0, 0)][DBLP ] Conf ] Jay K. Adams , Donald E. Thomas The Design of Mixed Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Vercauteren , Bill Lin , Hugo De Man Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nguyen-Ngoc Bình , Masaharu Imai , Akichika Shiomi , Nobuyuki Hikichi A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sudhakar Muddu Analysis of RC Interconnections Under Ramp Input. [Citation Graph (0, 0)][DBLP ] Conf ] Bernie Sheehan An AWE Technique for Fast Printed Circuit Board Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Florentin Dartu , Bogdan Tutuianu , Lawrence T. Pileggi RC-Interconnect Macromodels for Timing Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Kan Cheng , Chin-Chi Teng , Abhijit Dharchoudhury , Elyse Rosenbaum , Sung-Mo Kang iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch Techniques for Verifying Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy R. Levitt , Kunle Olukotun A Scalable Formal Verification Methodology for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] C. Norris Ip , David L. Dill State Reduction Using Reversible Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Felice Balarin , Harry Hsieh , Attila Jurecska , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Formal Verification of Embedded Systems based on CFSM Networks. [Citation Graph (0, 0)][DBLP ] Conf ] E. Berrebi , Polen Kission , Serge Vernalde , S. De Troch , J. C. Herluison , J. Fréhel , Ahmed Amine Jerraya , Ivo Bolsens Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] J. Huisken , F. Welten FADIC: Architectural Synthesis applied in IC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Tien-Chien Lee , Yu-Chin Hsu , Ben Chen , Masahiro Fujita Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Araujo , Sharad Malik , Mike Tien-Chien Lee Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Clifford Liem , Pierre G. Paulin , Ahmed Amine Jerraya Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kei Suzuki , Alberto L. Sangiovanni-Vincentelli Efficient Software Performance Estimation Methods for Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan Tutuianu , Florentin Dartu , Lawrence T. Pileggi An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. [Citation Graph (0, 0)][DBLP ] Conf ] V. Chandramouli , Karem A. Sakallah Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Neves , Eby G. Friedman Optimal Clock Skew Scheduling Tolerant to Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Matsunaga An Efficient Equivalence Checker for Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jagesh V. Sanghavi , Rajeev K. Ranjan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli High Performance BDD Package By Exploiting Memory Hiercharchy. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Stornetta , Forrest Brewer Implementation of an Efficient Parallel BDD Package. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Manpreet Khaira , Xudong Zhao Word Level Model Checking - Avoiding the Pentium FDIV Error. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Pandey , Richard Raimi , Derek L. Beatty , Randal E. Bryant Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Ilan Beer , Shoham Ben-David , Cindy Eisner , Avner Landver RuleBase: An Industry-Oriented Formal Verification Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant Bit-Level Analysis of an SRT Divider Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ásgeir Th. Eiríksson Integrating Formal Verification Methods with A Conventional Project Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Vercauteren , Bill Lin , Hugo De Man A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Benny Schnaider , Einat Yogev Software Development in a Hardware Simulation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Vojin Zivojnovic , Heinrich Meyr Compiled HW/SW Co-Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Radu Marculescu , Massoud Pedram Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin Energy Characterization based on Clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Soha Hassoun , Carl Ebeling Architectural Retiming: Pipelining Latency-Constrained Circuts. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak Optimizing Systems for Effective Block-Processing: The k -Delay Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , C. L. Liu Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yean-Yow Hwang Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Legl , Bernd Wurth , Klaus Eckl A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Ramsey W. Haddad , Srilatha Manne New Algorithms for Gate Sizing: A Comparative Study. [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Sato , Masamichi Kawarabayashi , Hideyuki Emura , Naotaka Maeda Post-Layout Optimization for Deep Submicron Design. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Enrico Malavasi Enhanced Network Flow Algorithm for Yield Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Chi Teng , Yi-Kan Cheng , Elyse Rosenbaum , Sung-Mo Kang Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van Genderen , N. P. van der Meijs Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] P. J. H. Elias , N. P. van der Meijs Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas J. Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Sahm , Claus Mayer , Jörg Pleickhardt , Johannes Schuck , Stefan Späth VDHL Development System and Coding Standard. [Citation Graph (0, 0)][DBLP ] Conf ] De-Sheng Chen , Majid Sarrafzadeh An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Rohfleisch , Alfred Kölbl , Bernd Wurth Reducing Power Dissipation after Technology Mapping by Structural Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Xiangfeng Chen , Peichen Pan , C. L. Liu Desensitization for Power Reduction in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luc Burgun , Frédéric Reblewski , Gérard Fenelon , Jean Barbier , Olivier Lepape Serial Fault Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel Partial Scan Design Based on Circuit State Information. [Citation Graph (0, 0)][DBLP ] Conf ] Laurence Goodby , Alex Orailoglu Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Aurobindo Dasgupta , Ramesh Karri Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Arun N. Lokanathan , Jay B. Brockman , John E. Renaud A Methodology for Concurrent Fabrication Process/Cell Library Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Mien Li , Linda S. Milor Computing Parametric Yield Adaptively Using Local Linear Models. [Citation Graph (0, 0)][DBLP ] Conf ] 