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Conferences in DBLP

Design Automation Conference (DAC) (dac)
1999 (conf/dac/99)

  1. Jing-Rebecca Li, Frank Wang, Jacob White
    An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:1-6 [Conf]
  2. Chung-Ping Chen, D. F. Wong
    Error Bounded Padé Approximation via Bilinear Conformal Transformation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:7-12 [Conf]
  3. Pavan K. Gunupudi, Michel S. Nakhla
    Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:13-16 [Conf]
  4. Bernard N. Sheehan
    ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:17-21 [Conf]
  5. Mukul R. Prasad, Philip Chong, Kurt Keutzer
    Why is ATPG Easy? [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:22-28 [Conf]
  6. Rolf Drechsler, Wolfgang Günther
    Using Lower Bounds During Dynamic BDD Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:29-32 [Conf]
  7. Gang Qu, Jennifer L. Wong, Miodrag Potkonjak
    Optimization-Intensive Watermarking Techniques for Decision Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:33-36 [Conf]
  8. Ali Dasdan, Sandy Irani, Rajesh K. Gupta
    Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:37-42 [Conf]
  9. Daniel Gajski
    IP-based Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:43- [Conf]
  10. Pai H. Chou, Ross B. Ortega, Ken Hines, Kurt Partridge, Gaetano Borriello
    ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:44-49 [Conf]
  11. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Virtual Simulation of Distributed IP-based Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:50-55 [Conf]
  12. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-Case Computation: A High-Level Technique for Power and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:56-61 [Conf]
  13. Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang
    Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:62-67 [Conf]
  14. Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
    Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:68-71 [Conf]
  15. Vijay Sundararajan, Keshab K. Parhi
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:72-75 [Conf]
  16. Raul Camposano, Kurt Keutzer, Jerry Fiddler, Alberto L. Sangiovanni-Vincentelli, Jim Lansford
    HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:76-77 [Conf]
  17. Xiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan
    Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:78-83 [Conf]
  18. Jiang Hu, Sachin S. Sapatnekar
    FAR-DS: Full-Plane AWE Routing with Driver Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:84-89 [Conf]
  19. Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
    Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:90-95 [Conf]
  20. Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:96-99 [Conf]
  21. Prashant Saxena, C. L. Liu
    Crosstalk Minimization Using Wire Perturbations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:100-103 [Conf]
  22. Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
    Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:104-109 [Conf]
  23. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:110-115 [Conf]
  24. Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
    CAD Directions for High Performance Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:116-121 [Conf]
  25. Jörg Henkel
    A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:122-127 [Conf]
  26. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:128-133 [Conf]
  27. Youngsoo Shin, Kiyoung Choi
    Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:134-139 [Conf]
  28. Wen-Tsong Shiue, Chaitali Chakrabarti
    Memory Exploration for Low Power, Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:140-145 [Conf]
  29. Ravi Sharma
    Distributed Application Development with Inferno. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:146-150 [Conf]
  30. David Stepner, Nagarajan Rajan, David Hui
    Embedded Application Design Using a Real-Time OS. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:151-156 [Conf]
  31. Ken Arnold
    The Jini Architecture: Dynamic Services in a Flexible Network. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:157-162 [Conf]
  32. Dennis Abts, Mike Roberts
    Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:163-168 [Conf]
  33. Jian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu
    Functional Verification of the Equator MAP1000 Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:169-174 [Conf]
  34. Shmuel Ur, Yaov Yadin
    Micro Architecture Coverage Directed Generation of Test Programs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:175-180 [Conf]
  35. You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung
    Verification of a Microprocessor Using Real World Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:181-184 [Conf]
  36. David Van Campenhout, Trevor N. Mudge, John P. Hayes
    High-Level Test Generation for Design Verification of Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:185-188 [Conf]
  37. Laurent Fournier, Anatoly Koyfman, Moshe Levinger
    Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:189-194 [Conf]
  38. Roland W. Freund
    Passive Reduced-Order Models for Interconnect Simulation and Their Computation via Krylov-Subspace Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:195-200 [Conf]
  39. Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
    Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:201-206 [Conf]
  40. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    Robust Rational Function Approximation Algorithm for Model Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:207-212 [Conf]
  41. Reinaldo A. Bergamaschi
    Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:213-218 [Conf]
  42. Jianwen Zhu, Daniel Gajski
    Soft Scheduling in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:219-224 [Conf]
  43. Marek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko
    Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:225-230 [Conf]
  44. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Maximizing Performance by Retiming and Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:231-236 [Conf]
  45. Klaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl
    A Practical Approach to Multiple-Class Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:237-242 [Conf]
  46. Peichen Pan
    Performance-Driven Integration of Retiming and Resynthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:243-246 [Conf]
  47. Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:247-252 [Conf]
  48. Joseph A. Fisher
    Customized Instruction-Sets for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:253-257 [Conf]
  49. Samuel P. Harbison
    System-Level Hardware/Software Trade-offs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:258-259 [Conf]
  50. Jonah McLeod, Nozar Azarakhsh, Glen Ewing, Paul Gingras, Scott Reedstrom, Chris Rowen
    Functional Verification - Real Users, Real Problems, Real Opportunities (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:260-261 [Conf]
  51. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:262-267 [Conf]
  52. Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura
    An O-Tree Representation of Non-Slicing Floorplan and Its Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:268-273 [Conf]
  53. Florin Balasa, Koen Lampaert
    Module Placement for Analog Layout Using the Sequence-Pair Representation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:274-279 [Conf]
  54. Martin Grajcar
    Genetic List Scheduling Algorithm for Scheduling and Allocation on a Loosely Coupled Heterogeneous Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:280-285 [Conf]
  55. Sanghun Park, Kiyoung Choi
    Performance-Driven Scheduling with Bit-Level Chaining. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:286-291 [Conf]
  56. Steve Haynal, Forrest Brewer
    A Model for Scheduling Protocol-Constrained Components and Environments. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:292-295 [Conf]
  57. Luiz C. V. dos Santos, Jochen A. G. Jess
    A Reordering Technique for Efficient Code Motion. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:296-299 [Conf]
  58. Yatin Vasant Hoskote, Timothy Kam, Pei-Hsin Ho, Xudong Zhao
    Coverage Estimation for Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:300-305 [Conf]
  59. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Improving Symbolic Traversals by Means of Activity Profiles. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:306-311 [Conf]
  60. Shankar G. Govindaraju, David L. Dill, Jules P. Bergmann
    Improved Approximate Reachability Using Auxiliary State Variables. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:312-316 [Conf]
  61. Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu
    Symbolic Model Checking Using SAT Procedures instead of BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:317-320 [Conf]
  62. Johnson Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak
    Power Efficient Mediaprocessors: Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:321-326 [Conf]
  63. Arnout Vandecappelle, Miguel Miranda, Erik Brockmeyer, Francky Catthoor, Diederik Verkest
    Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:327-332 [Conf]
  64. Lode Nachtergaele, Bart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Ivo Bolsens
    Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:333-336 [Conf]
  65. Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels
    A 10 Mbit/s Upstream Cable Modem with Automatic equalization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:337-340 [Conf]
  66. Kurt Keutzer, Kurt Wolf, David Pietromonaco, Jay Maxey, Jeff Lewis, Martin Lefebvre, Jeff Burns
    Panel: Cell Libraries - Build vs. Buy; Static vs. Dynamic. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:341-342 [Conf]
  67. George Karypis, Vipin Kumar
    Multilevel k-way Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:343-348 [Conf]
  68. Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:349-354 [Conf]
  69. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph Partitioning with Fixed Vertices. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:355-359 [Conf]
  70. Sung-Woo Hur, John Lillis
    Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:360-366 [Conf]
  71. Sumit Roy, Krishna P. Belkhale, Prithviraj Banerjee
    An Approxmimate Algorithm for Delay-Constraint Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:367-372 [Conf]
  72. Jason Cong, Yean-Yow Hwang, Songjie Xu
    Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:373-378 [Conf]
  73. Priyadarshan Patra, Unni Narayanan
    Automated Phase Assignment for the Synthesis of Low Power Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:379-384 [Conf]
  74. Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann
    Enhancing Simulation with BDDs and ATPG. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:385-390 [Conf]
  75. Valeria Bertacco, Maurizio Damiani, Stefano Quer
    Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:391-396 [Conf]
  76. Miroslav N. Velev, Randal E. Bryant
    Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:397-401 [Conf]
  77. Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
    Parametric Representations of Boolean Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:402-407 [Conf]
  78. Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass
    Vertical Benchmarks for CAD. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:408-413 [Conf]
  79. Xiaobo Hu, Garrison W. Greenwood, S. Ravichandran, Gang Quan
    A Framework for User Assisted Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:414-419 [Conf]
  80. Benoit Clement, Richard Hersemeule, Etienne Lantreibecq, Bernard Ramanadin, Pierre Coulomb, François Pogodalla
    Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:420-424 [Conf]
  81. Johann Notbauer, Thomas W. Albrecht, Georg Niedrist, Stefan Rohringer
    Verification and Management of a Multimillion-Gate Embedded Core Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:425-428 [Conf]
  82. Paul D. Franzon, Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker
    Parasitic Extraction Accuracy - How Much is Enough? [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:429- [Conf]
  83. Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
    Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:430-435 [Conf]
  84. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
    Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:436-441 [Conf]
  85. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
    Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:442-445 [Conf]
  86. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:446-451 [Conf]
  87. Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan
    Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:452-459 [Conf]
  88. Jason Cong, Honching Li, Chang Wu
    Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:460-465 [Conf]
  89. Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long
    Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:466-471 [Conf]
  90. Amir H. Salek, Jinan Lou, Massoud Pedram
    MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:472-478 [Conf]
  91. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion with Accurate Gate and Interconnect Delay Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:479-484 [Conf]
  92. Joon-Seo Yim, Chong-Min Kyung
    Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:485-490 [Conf]
  93. Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
    A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:491-496 [Conf]
  94. Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro
    Improved Selay Prediction for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:497-501 [Conf]
  95. Chung-Ping Chen, Noel Menezes
    Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:502-506 [Conf]
  96. Jason Cong, David Zhigang Pan
    Interconnect Estimation and Dlanning for Deep Submicron Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:507-510 [Conf]
  97. Luciano Lavagno, Ellen Sentovich
    ECL: A Specification Environment for System-Level Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:511-516 [Conf]
  98. Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich
    Representation of Function Variants for Embedded System Optimization and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:517-522 [Conf]
  99. Jules P. Bergmann, Mark Horowitz
    Vex - A CAD Toolbox. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:523-528 [Conf]
  100. Juan Antonio Carballo, Stephen W. Director
    Constraint Management for Collaborative Electronic Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:529-534 [Conf]
  101. Kristofer S. J. Pister, Albert P. Pisano, Nicholas Swart, Mike Horton, John Rychcik, John R. Gilbert, Gerry K. Fedder
    MEMS CAD Beyond Multi-Million Transistors (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:535-536 [Conf]
  102. Johannes Tausch, Jacob K. White
    A Multiscale Method for Fast Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:537-542 [Conf]
  103. Vikram Jandhyala, Scott Savage, J. Eric Bracken, Zoltan J. Cendes
    Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface Meshes. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:543-548 [Conf]
  104. Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang
    Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:549-554 [Conf]
  105. Qinru Qiu, Massoud Pedram
    Dynamic Power Management Based on Continuous-Time Markov Decision Processes. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:555-561 [Conf]
  106. Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
    Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:562-567 [Conf]
  107. Milos D. Ercegovac, Darko Kirovski, Miodrag Potkonjak
    Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:568-573 [Conf]
  108. Daniel Geist, Giora Biran, Tamarah Arons, Michael Slavkin, Yvgeny Nustov, Monica Farkas, Karen Holtz, Andy Long, Dave King, Steve Barret
    A Methodology for the Verification of a ``System on Chip''. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:574-579 [Conf]
  109. Ing-Jer Huang, Tai-An Lu
    ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:580-585 [Conf]
  110. Christos A. Papachristou, F. Martin, Mehrdad Nourani
    Microprocessor Based Testing for Core-Based System on Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:586-591 [Conf]
  111. Hema Kapadia, Mark Horowitz
    Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:592-597 [Conf]
  112. Imed Moussa, Zoltan Sugar, Rodolph Suescun, Mario Diaz-Nava, Marco Pavesi, Salvatore Crudo, Luca Gazi, Ahmed Amine Jerraya
    Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:598-603 [Conf]
  113. Darko Kirovski, Miodrag Potkonjak
    Engineering Change: Methodology and Applications to Behavioral and System Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:604-609 [Conf]
  114. André DeHon, John Wawrzynek
    Reconfigurable Computing: What, Why, and Implications for Design Automation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:610-615 [Conf]
  115. Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
    An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:616-622 [Conf]
  116. Alexandro M. S. Adário, Eduardo L. Roehe, Sergio Bampi
    Dynamically Reconfigurable Architecture for Image Processor Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:623-628 [Conf]
  117. Onuttom Narayan, Jaijeet S. Roychowdhury
    Multi-Time Simulation of Voltage-Controlled Oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:629-634 [Conf]
  118. Dan Feng, Joel R. Phillips, Keith Nabors, Kenneth S. Kundert, Jacob White
    Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:635-640 [Conf]
  119. Ognen J. Nastov, Jacob White
    Time-Mapped Harmonic Balance. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:641-646 [Conf]
  120. Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham
    Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:647-652 [Conf]
  121. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:653-659 [Conf]
  122. Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
    Multiple Error Diagnosis Based on Xlists. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:660-665 [Conf]
  123. Farzan Fallah, Pranav Ashar, Srinivas Devadas
    Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:666-671 [Conf]
  124. Lionel Bening
    A Two-State Methodology for RTL Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:672-677 [Conf]
  125. Cordula Hansen, Francisco Nascimento, Wolfgang Rosenstiel
    An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:678-683 [Conf]
  126. Miron Abramovici, José T. de Sousa, Daniel G. Saab
    A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:684-690 [Conf]
  127. Fatih Kocan, Daniel G. Saab
    Dynamic Fault Diagnosis on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:691-696 [Conf]
  128. Xiaohan Zhu, Bill Lin
    Hardware Compilation for FPGA-Based Configurable Computing Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:697-702 [Conf]
  129. D. J. Eaglesham
    0.18m CMOS and Beyond. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:703-708 [Conf]
  130. Ching-Te Chuang, Ruchir Puri
    SOI Digital CMOS VLSI - a Design Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:709-714 [Conf]
  131. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Equivalent Elmore Delay for RLC Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:715-720 [Conf]
  132. Yehea I. Ismail, Eby G. Friedman
    Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:721-724 [Conf]
  133. Abdallah Tabbara, Robert K. Brayton, A. Richard Newton
    Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:725-730 [Conf]
  134. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah
    Functional Timing Analysis for IP Characterization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:731-736 [Conf]
  135. Richard Raimi, Jacob A. Abraham
    Detecting False Timing Paths: Experiments on PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:737-741 [Conf]
  136. Han Bin Kim, Dong Sam Ha, Takeshi Takahashi
    On ILP Formulations for Built-In Self-Testable Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:742-747 [Conf]
  137. Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
    Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:748-753 [Conf]
  138. Irith Pomeranz, Sudhakar M. Reddy
    Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:754-759 [Conf]
  139. Yi-Min Jiang, Kwang-Ting Cheng
    Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:760-765 [Conf]
  140. Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
    A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:766-771 [Conf]
  141. Ramesh Harjani, Bapiraju Vinnakota
    Digital Aetection of Analog Parametric Faults in SC Filters. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:772-777 [Conf]
  142. Dyson Wilkes, M. M. Kamal Hashmi
    Application of High Level Interface-Based Design to Telecommunications System Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:778-783 [Conf]
  143. Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels, Ivo Bolsens
    Hardware Reuse at the Behavioral Level. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:784-789 [Conf]
  144. Tommy Kuhn, Wolfgang Rosenstiel, Udo Kebschull
    Description and Simulation of Hardware/Software Systems with Java. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:790-793 [Conf]
  145. Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
    Java Driven Codesign and Prototyping of Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:794-797 [Conf]
  146. Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser
    Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:798- [Conf]
  147. Andrew B. Kahng, Y. C. Pati
    Subwavelength Lithography and Its Potential Impact on Design and EDA. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:799-804 [Conf]
  148. Marco Sgroi, Luciano Lavagno
    Synthesis of Embedded Software Using Free-Choice Petri Nets. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:805-810 [Conf]
  149. Ying Zhao, Sharad Malik
    Exact Memory Size Estimation for Array Computations without Loop Unrolling. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:811-816 [Conf]
  150. Steven Bashford, Rainer Leupers
    Constraint Driven Code Selection for Fixed-Point DSPs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:817-822 [Conf]
  151. Alain Pegatoquet, Emmanuel Gresset, Michel Auguin, Luc Bianco
    Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:823-826 [Conf]
  152. Asawaree Kalavade, Joe Othmer, Bryan D. Ackland, Kanwar Jit Singh
    Software Environment for a Multiprocessor DSP. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:827-830 [Conf]
  153. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:831-836 [Conf]
  154. Arlindo L. Oliveira
    Robust Techniques for Watermarking Sequential Circuit Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:837-842 [Conf]
  155. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
    Effective Iterative Techniques for Fingerprinting Design IP. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:843-848 [Conf]
  156. Inki Hong, Miodrag Potkonjak
    Behavioral Synthesis Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:849-854 [Conf]
  157. James Goodman, Anantha Chandrakasan, Abram P. Dancy
    Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:855-860 [Conf]
  158. Massoud Pedram, Qing Wu
    Design Considerations for Battery-Powered Electronics. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:861-866 [Conf]
  159. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Cycle-Accurate Simulation of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:867-872 [Conf]
  160. Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist
    Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:873-878 [Conf]
  161. Timothy P. Kurzweg, Steven P. Levitan, Philippe J. Marchand, Jose A. Martinez, Kurt R. Prough, Donald M. Chiarulli
    A CAD Tool for Optical MEMS. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:879-884 [Conf]
  162. Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu
    On Thermal Effects in Deep Sub-Micron VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:885-891 [Conf]
  163. D. Allen, D. Behrends, B. Stanisic
    Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:892-897 [Conf]
  164. Gangadhar Konduri, Anantha Chandrakasan
    A Framework for Collaborative and Distributed Web-Based Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:898-903 [Conf]
  165. Phillip Restle, Albert E. Ruehli, Steven G. Walker
    Dealing with Inductance in High-Speed Chip Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:904-909 [Conf]
  166. Mattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luis Miguel Silveira, Jacob White
    Interconnect Analysis: From 3-D Structures to Circuit Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:910-914 [Conf]
  167. Michael W. Beattie, Lawrence T. Pileggi
    IC Analyses Including Extracted Inductance Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:915-920 [Conf]
  168. Shannon V. Morton
    On-Chip Inductance Issues in Multiconductor Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:921-926 [Conf]
  169. George Hadjiyiannis, Pietro Russo, Srinivas Devadas
    A Methodology for Accurate Performance Evaluation in Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:927-932 [Conf]
  170. Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr
    LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:933-938 [Conf]
  171. Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung
    Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:939-944 [Conf]
  172. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley
    MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:945-950 [Conf]
  173. Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
    Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:951-957 [Conf]
  174. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:958-963 [Conf]
  175. Lisa Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic
    Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:964-969 [Conf]
  176. Mike Benjamin, Daniel Geist, Alan Hartman, Gérard Mas, Ralph Smeets, Yaron Wolfsthal
    A Study in Coverage-Driven Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:970-975 [Conf]
  177. Wanli Jiang, Bapiraju Vinnakota
    IC Test Using the Energy Consumption Ratio. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:976-981 [Conf]
  178. C. Patrick Yue, S. Simon Wong
    Design Strategy of On-Chip Inductors for Highly Integrated RF Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:982-987 [Conf]
  179. N. R. Belk, M. R. Frei, M. Tsai, A. J. Becker, K. L. Tokuda
    The Simulation and Design of Integrated Inductors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:988-993 [Conf]
  180. Maria del Mar Hershenson, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee
    Optimization of Inductor Circuits via Geometric Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:994-998 [Conf]
  181. Richard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani
    Panel: What is the Proper System on Chip Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:999- [Conf]
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NOTICE2
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