Conferences in DBLP
L.-T. Wang , Nathan E. Hoover , Edwin H. Porter , John J. Zasio SSIM: A Software Levelized Compiled-Code Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant , Derek L. Beatty , Karl S. Brace , K. Cho , Thomas J. Sheffler COSMOS: A Compiled Simulator for MOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] S. B. Tan , K. Totton , Keith Baker , Prab Varma , R. Porter A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nikrouz Faroughi , Michael A. Shanblatt An Improved Systematic Method for Constructing Systolic Arrays from Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Jain , Alice C. Parker , Nohbyung Park Predicting Area-Time Tradeoffs for Pipelined Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Harjani , Rob A. Rutenbar , L. Richard Carley A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] M. C. Chi An Automatic Rectilinear Partitioning Procedure for Standard Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Lov K. Grover Standard Cell Placement Using Simulated Sintering. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph-Michael Kling , Prithviraj Banerjee ESP: A New Standard Cell Placement Package Using Simulated Evolution. [Citation Graph (0, 0)][DBLP ] Conf ] V. Masurkar Requirements for a Practical Software Engineering Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan B. Rosenberg The Making of VIVID: A Software Engineering Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] N. J. Elias A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Vladimirescu , David Weiss , Manolis Katevenis , Zvika Bronstein , Alon Kifir , Karja Danuwidjaja , K. C. Ng , Niraj Jain , Steve Lass A Vector Hardware Accelerator with Circuit Simulation Emphasis. [Citation Graph (0, 0)][DBLP ] Conf ] M. T. Smith A Hardware Switch Level Simulator for Large MOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal , William J. Dally , Ahmed K. Ezzat , W. C. Fischer , H. V. Jagadish , A. S. Krishnakumar Architecture and Design of the MARS Hardware Accelerator. [Citation Graph (0, 0)][DBLP ] Conf ] Donald M. Webber , Alberto L. Sangiovanni-Vincentelli Circuit Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Kye S. Hedlund Aesop: A Tool for Automated Transistor Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Mehmet A. Cirit Transistor Sizing in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Hofmann , J. K. Kim Delay Optimization of Combinational Static CMOS Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Robert E. Canright , A. R. Helland Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic. [Citation Graph (0, 0)][DBLP ] Conf ] J. Royle , Mikael Palczewski , H. VerHeyen , N. Naccache , Jiri Soukup Geometrical Compaction in One Dimension for Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] D. B. Polkl A Three-Layer Gridless Channel Router with Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] H. H. Chen Routing L-Shaped Channels in Nonslicing-Structure Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas J. Naclerio , Sumio Masuda , Kazuo Nakajima Via Minimization for Gridless Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Louise Trevillyan An Overview of Logic Synthesis Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly Realistic Fault Modeling for VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Smith , M. Ray Mercer , B. Brodk Demand Driven Simulation: BACKSIM. [Citation Graph (0, 0)][DBLP ] Conf ] J. W. Smith , K. S. Smith , Robert J. Smith II Faster Architectural Simulation Through Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre G. Paulin , John P. Knight Force-Directed Scheduling in Automatic Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Forrest Brewer , Daniel Gajski Knowledge Based Control in Micro-Architecture Design. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi J. Kurdahi , Alice C. Parker REAL: a program for REgister ALlocation. [Citation Graph (0, 0)][DBLP ] Conf ] R. K. McGehee A Practical Moat Router. [Citation Graph (0, 0)][DBLP ] Conf ] S. Chowdhury An Automated Design of Minimum-Area IC Power/Ground Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Steven T. Healey , William J. Kubitz Abstract Routing of Logic Networks for Custom Module Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael H. Schultz , Franc Brglez Accelerated Transition Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Rochit Rajsuman , Yashwant K. Malaiya , Anura P. Jayasumana On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates. [Citation Graph (0, 0)][DBLP ] Conf ] S. E. Concina , G. S. Liu Integrating Design Information for IC Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] R. M. McDermott , D. Stern Switch Directed Dynamic Causal Networks - a Paradigm for Electronic System Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Weise Functional Verification of MOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton On the Verification of Sequential Machines at Differing Levels of Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Mandalagiri S. Chandrasekhar , J. P. Privitera , K. W. Conradt Application of Term Rewriting Techniques to Hardware Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Hi-Keung Tony Ma , Srinivas Devadas , Alberto L. Sangiovanni-Vincentelli , R. Wei Logic Verification Algorithms and Their Parallel Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] C. W. Carpenter , Mark Horowitz Generating Incremental VLSI Compaction Spacing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao-Ming Xiong , Ernest S. Kuh Nutcracker: An Efficient and Intelligent Channel Spacer. [Citation Graph (0, 0)][DBLP ] Conf ] Lars S. Nyland , Stephen W. Daniel , D. Rogers Improving Virtual-Grid Compaction Through Grouping. [Citation Graph (0, 0)][DBLP ] Conf ] B. Lin , A. Richard Newton KAHLUA: A Hierarchical Circuit Disassembler. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan Preas Benchmarks for Cell-Based Layout Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Bhateja , Randy H. Katz VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data. [Citation Graph (1, 0)][DBLP ] Conf ] Arnon Rosenthal , Sandra Heiler Querying Part Hierarchies: A Knowledge-Based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Sandra Heiler , Umeshwar Dayal , Jack A. Orenstein , S. Radke-Sproull An Object-Oriented Approach to Data Management: Why Design Databases Need It. [Citation Graph (1, 0)][DBLP ] Conf ] Kurt Keutzer DAGON: Technology Binding and Local Optimization by DAG Matching. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Beekman , Robert Michael Owens , Mary Jane Irwin Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. Friedman , Kenneth J. Supowit Finding the Optimal Variable Ordering for Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] J. Apte , Gershon Kedem Strip Layout: A New Layout Methodology for Standard Circuit Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Schuck , Norbert Wehn , Manfred Glesner , G. Kamp The ALGIC Silicon Compiler System: Implementation, Design Experience and Results. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wei-Ming Dai , Masao Sato , Ernest S. Kuh A Dynamic and Efficient Representation of Building-Block Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Yeh Liu , Kewal K. Saluja , Shambhu J. Upadhyaya BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Joachim Wunderlich On Computing Optimized Input Probabilities for Random Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Philip S. Yu , C. Mani Krishna , Yann-Hang Lee VLSI Circuit Testing Using an Adaptive Optimization Model. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski , Slawomir Pilarski Circular Self-Test Path: A Low-Cost BIST Technique. [Citation Graph (0, 0)][DBLP ] Conf ] John J. Granacki Jr. , Alice C. Parker PHRAN-SPAN: A Natural Language Interface for System Specifications. [Citation Graph (1, 0)][DBLP ] Conf ] W. Lee , G. Liu , K. Peterson TED: A Graphical Technology Description Editor. [Citation Graph (0, 0)][DBLP ] Conf ] W. Lee "?": A Context-Sensitive Help System Based on Hypertext. [Citation Graph (0, 0)][DBLP ] Conf ] R. K. Chun , K.-J. Chang , Lawrence P. McNamee VISION: VHDL Induced Schematic Imaging on Net-Lists. [Citation Graph (0, 0)][DBLP ] Conf ] D. L. Johannsen , S. K. Tsubota , K. McElvain An Intelligent Compiler Subsystem for a Silicon Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Bertrand Serlet Fast, Small, and Static Combinatorial CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] P. A. Subrahmanyam LCS - A Leaf Cell Synthesizer Employing Formal Deduction Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. J. Chen , D. Y. Chen A Design Rule Independent Cell Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] M. Shahdad An Interface between VHDL and EDIF. [Citation Graph (0, 0)][DBLP ] Conf ] C. H. Parks Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] L. F. Saunders The IBM VHDL Design System. [Citation Graph (0, 0)][DBLP ] Conf ] J. Hines Where VHDL Fits Within the CAD Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Susheel J. Chandra , Janak H. Patel A Hierarchical Approach Test Vector Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Tom E. Kirkland , M. Ray Mercer A Topological Search Algorithm for ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ladjadj , J. F. McDonald Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Michael Owens , Mary Jane Irwin An Overview of the Penn State Design System. [Citation Graph (0, 0)][DBLP ] Conf ] Shigenobu Suzuki , Tatsushige Bitoh , Masao Kakimoto , Kazutoshi Takahashi , Takao Sugimoto TRIP: An Automated Technology Mapping System. [Citation Graph (0, 0)][DBLP ] Conf ] T. Ogihara , H. Toyoshima , S. Murai ASTA: LSI Design Management System. [Citation Graph (0, 0)][DBLP ] Conf ] D. F. Wong , C. L. Liu Array Optimization for VLSI Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] R. L. Maiasz , John P. Hayes Layout Optimization of CMOS Functional Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Y.-C. Chang , S. C. Chang , L.-H. Hsu Automated Layout Generation Using Gate Matrix Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Waxman The Design Automation Standards Environment. [Citation Graph (0, 0)][DBLP ] Conf ] L. O'Connell Design Automation Standards Need Integration. [Citation Graph (0, 0)][DBLP ] Conf ] R. J. Pachter Design Automation Standards - Perspectives from a Down-the-Road End User. [Citation Graph (0, 0)][DBLP ] Conf ] M. L. Brei Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Shun-Lin Su , Vasant B. Rao , Timothy N. Trick HPEX: A Hierarchical Parasitic Circuit Extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Don Stark , Mark Horowitz RED: Resistance Extraction for Digital Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jung-Gen Wu , William P.-C. Ho , Yu Hen Hu , David Y. Y. Yun , H. J. Yu Function Search from Behavioral Description of a Digital System. [Citation Graph (0, 0)][DBLP ] Conf ] C. Kingsley The Implementation of a State Machine Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Edward P. Stabler , H. Bingol Boolean Comparison by Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Larry Soulé , R. Blank Statistics for Parallelism and Abstraction Level in Digital Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Steven S. Leung , Michael A. Shanblatt A Conceptual Framework for Designing ASIC Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Dick C. A. Bulterman CASE: An Integrated Design Environment for Algorithm-Driven Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] R. Galivanche , Sudhakar M. Reddy A Parallel PLA Minimization Program. [Citation Graph (0, 0)][DBLP ] Conf ] Chidchanok Lursinsap , Daniel Gajski Improving a PLA Area by Pull-Up Transistor Folding. [Citation Graph (0, 0)][DBLP ] Conf ] L. B. Nguyen , M. A. Perkowdki , N. B. Goldstein PALMINI - Fast Boolean Minimizer for Personal Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey On Yield Consideration for the Design of Redundant Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] D. Kaplan Routing with a Scanning Window-8Ma Unified Approach. [Citation Graph (0, 0)][DBLP ] Conf ] C. H. Ng A "gridless" Variable-Width Channel Router for Marco Cell Design. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Enbody , H. C. Du General Purpose Router. [Citation Graph (0, 0)][DBLP ] Conf ] Y. C. Hsu , Y. Pan , William J. Kubitz A Path Selection Global Router. [Citation Graph (0, 0)][DBLP ] Conf ] P. C. Shah , Hosaker N. Mahabala A New Compaction Scheme Based on Compression Ridges. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Becker , Günter Hotz , Reiner Kolla , Paul Molitor , Hans-Georg Osthof Hierarchical Design Based on a Calculus of Nets. [Citation Graph (0, 0)][DBLP ] Conf ] E. F. M. Kouka , Gabriele Saucier An Application of Exploratory Data Analysis Techniques to Floorplan Design. [Citation Graph (0, 0)][DBLP ] Conf ] W.-J. Lue , Lawrence P. McNamee PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement. [Citation Graph (0, 0)][DBLP ] Conf ] T. Cesear , E. Iodice , C. Tsareff PAMS: An Expert System for Parameterized Module Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Y.-L. S. Lin , Daniel Gajski LES: A Layout Expert System. [Citation Graph (0, 0)][DBLP ] Conf ] R. L. Steele An Expert System Application in Semicustom VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Pinaki Mazumder , Janak H. Patel , W. Kent Fuchs Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Krishnamurthy A Dynamic Programming Approach to the Test Point Insertion Problem. [Citation Graph (0, 0)][DBLP ] Conf ] D. Praizler , G. Fritz A Parts Selection Expert System to Increase Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] J. Y. Tou , W. H. Ki , K. C. Fan , C. L. Huang Knowledge Based Approach for the Verification of CAD Database Generated by an Automated Schematic Capture System. [Citation Graph (0, 0)][DBLP ] Conf ] E. Rosenberg A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Dion Fast Printed Circuit Board Routing. [Citation Graph (0, 0)][DBLP ] Conf ] R. Forbes Heuristic Acceleration of Force-Directed Placement. [Citation Graph (0, 0)][DBLP ] Conf ] J. D. Morison , N. E. Peeling , T. L. Thorp , E. V. Whiting EASE: A Design Support Environment for the HDDL ELLA. [Citation Graph (0, 0)][DBLP ] Conf ] L.-P. Demers , P. Jacques , S. Fauvel , Eduard Cerny CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Emil F. Girczyc , Tai A. Ly STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony J. Gadient , J. L. Ebel Rational for and Organization of the Engineering Information System Program. [Citation Graph (0, 0)][DBLP ] Conf ] Ali A. Minai , Ronald D. Williams , F. W. Blake A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Gotaro Odawara , T. Hamuro , Kazuhiko Iijima , T. Yoshino , Y. Dai A Rule-Based Placement System for Printed Wiring Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Farn Eric Wu , Anthony S. Wojcik , Lionel M. Ni A Rule-Based Circuit Representation for Automated CMOS Design and Verification. [Citation Graph (0, 0)][DBLP ] Conf ] T. D. Spiers , D. A. Edwards A High Performance Routing Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Youngju Won , Sartaj Sahni , Yacoub M. El-Ziq A Hardware Accelerator for Maze Routing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Jones , Prithviraj Banerjee Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Kunle Olukotun , Trevor N. Mudge A Preliminary Investigation into Parallel Routing on a Hypercube Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Lathrop , Robert J. Hall , Robert S. Kirk Functional Abstraction from Structure in VLSI Simulation Models. [Citation Graph (0, 0)][DBLP ] Conf ] S. Koeppe Optimal Layout to Avoid CMOS Stuck-Open Faults. [Citation Graph (0, 0)][DBLP ] Conf ] 