Conferences in DBLP
Harish Kriplani , Farid N. Najm , Ibrahim N. Hajj Maximum Current Estimation in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Cheng Ju , Resve A. Saleh Incremental Circuit Simulation Using Waveform Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] T. A. Johnson , Albert E. Ruehli Parallel Waveform Relaxation of Circuits with Global Feedback Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Hi-Keung Tony Ma On the Over-Specification Problem in Sequential ATPG Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Krishna B. Rajan , David T. Miller Freeze!: A New Approach for Testing Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Charles Njinda , Melvin A. Breuer SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Andisheh Sarabi , Marek A. Perkowski Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Jean Christophe Madre Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Olivier Coudert , Jean Christophe Madre Symbolic Prime Generation for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Dwight D. Hill , Ewald Detjens FPGA Design Principles (A Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Lars W. Hagen , Andrew B. Kahng Net Partitions Yield Better Module Partitions. [Citation Graph (0, 0)][DBLP ] Conf ] Minshine Shih , Ernest S. Kuh , Ren-Song Tsay Performance-Driven System Partitioning on Multi-Chip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Takeo Hamada , Chung-Kuan Cheng , Paul M. Chau A Wire Length Estimation Technique Utilizing Neighborhood Density Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Chi Wang , D. F. Wong A Graph Theoretic Technique to Speed up Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Susmita Sur-Kolay , Bhargab B. Bhattacharya Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury , A. Richard Newton , Donald O. Pederson Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time. [Citation Graph (0, 0)][DBLP ] Conf ] Shen Lin , Ernest S. Kuh Transient Simulation of Lossy Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Raghavan , J. Eric Bracken , Ronald A. Rohrer AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems. [Citation Graph (0, 0)][DBLP ] Conf ] David D. Ling , S. Kim , J. White A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , Christos A. Papachristou Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Minjoong Rim , Rajiv Jain Representing Conditional Branches for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kazutoshi Wakabayashi , Hirohito Tanaka Global Scheduling Independent of Control Dependencies Based on Condition Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys Optimal Scheduling and Allocation of Embedded VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Minjoong Rim , Rajiv Jain , Renato De Leone Optimal Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Werner Geurts , Francky Catthoor , Hugo De Man Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Hillen Is Technology-Independent Design Really Practical? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] David Becker , Raj K. Singh , Stephen G. Tell An Engineering Environment for Hardware/Software Co-Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ing-Jer Huang , Alvin M. Despain High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. [Citation Graph (0, 0)][DBLP ] Conf ] SungHo Kim , Prithviraj Banerjee , Vivek Chickermane , Janak H. Patel APT: An Area-Performance-Testability Driven Placement Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Gao , Pravin M. Vaidya , C. L. Liu A Performance Driven Macro-Cell Placement Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Eugene Shragowitz Fuzzy Logic Approach to Placement Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Bhattacharya , Prathima Agrawal , Vishwani D. Agrawal Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty , Vishwani D. Agrawal , Michael L. Bushnell Delay Fault Models and Test Generation for Random Logic Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Saldanha , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy At-Speed Delay Testing of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf , Andrés Takach , Chun-Yao Huang , Richard Manno , Ephrem Wu The Princeton University Behavioral Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] A. Stoll , P. Duzy High-Level Synthesis from VHDL with Exact Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Seawright , Forrest Brewer Synthesis from Production-Based Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Collet Which ASIC Technology Will Dominate the 1990's (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Eli Chiprout , Michel S. Nakhla Generalized Moment-Matching Methods for Transient Analysis of Interconnect Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Demos F. Anastasakis , Nanda Gopal , Seok-Yoon Kim , Lawrence T. Pillage On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] John Y. Lee , Ronald A. Rohrer AWEsymbolic: Compiled Analysis of Linear(ized) Circuits using Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid , Daniel Gajski Specification Partitioning for System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Claudionor José Nunes Coelho Jr. , Giovanni De Micheli Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Hua Hung , Alice C. Parker High-Level Synthesis with Pin Constraints for Multiple-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] D. Sreenivasa Rao , Fadi J. Kurdahi Partitioning by Regularity Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-Lin Yu , P. A. Subrahmanyam A Path-Oriented Approach for Reducing Hazards in Asynchronous Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Saldanha , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. [Citation Graph (0, 0)][DBLP ] Conf ] Hsi-Chuan Chen , David Hung-Chang Du , Siu-Wing Cheng Circuit Enhancement by Eliminating Long False Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer , Jacob White Estimation of Average Switching Activity in Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] William Lattin Why Data Models Will Become the Fastest Growing Segment of the EDA Market (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jaushin Lee , Janak H. Patel Hierarchical Test Generation under Intensive Global Functional Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jean François Santucci , Gérard Dray , Norbert Giambiasi , Marc Boumédine A Methodology to Reduce the Computational Cost of Behavioral Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Vishakantaiah , Jacob A. Abraham , Magdy S. Abadir Automatic Test Knowledge Extraction from VHDL (ATKET). [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Krishnamoorthy , John A. Nestor Data Path Allocation using an Extended Binding Model. [Citation Graph (0, 0)][DBLP ] Conf ] Brent Gregory , Don MacMillen , Dennis Fogg ISIS: A System for Performance Driven Resource Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Elke A. Rundensteiner , Daniel Gajski Functional Synthesis Using Area and Delay Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rick Potter Why it doesn't work for CAD (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Gerry Langeler Directions to Watch in Design Technology (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep Batra , David Cooke Hcompare: A Hierarchical Netlist Comparison Program. [Citation Graph (0, 0)][DBLP ] Conf ] Georg Peltz An Interpreter for General Netlist Design Rule Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Ravi Varadarajan Hierarchical Pitchmatching Compaction Using Minimum Design. [Citation Graph (0, 0)][DBLP ] Conf ] David G. Boyer Process Independent Constraint Graph Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Wonjong Kim , Joohack Lee , Hyunchul Shin A New Hierarchical Layout Compactor Using Simplified Graph Models. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Ho Lee , Sudhakar M. Reddy On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Soumitra Bose , Prathima Agrawal Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung Ki Lee , Dong Sam Ha HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Amitava Majumdar , Sarma Sastry On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Kubiak , Steven Parkes , W. Kent Fuchs , Resve A. Saleh Exact Evaluation of Diagnostic Test Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Minshen Liu Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , Serge Pravossoudovitch A Novel Approach to Delay-Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Chung , Jonathan Rose TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Sawkar , Donald E. Thomas Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ulf Schlichtmann , Franc Brglez , Michael Hermann Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli An Improved Synthesis Algorithm for Multiplexor-Based PGA's. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick M. Hefferan , Steve Sapiro Acquiring and Maintaining State-of-the-Art DA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ichiang Lin , John A. Ludwig , Kwok Eng Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas G. Szymanski Computing Optimal Clock Schedules. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Kanwar Jit Singh , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli On the Temporal Equivalence of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tod Amon , Gaetano Borriello An Approach to Symbolic Timing Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit A. Gennart , David C. Luckham Validating Discrete Event Simulations Using Event Pattern Mappings. [Citation Graph (0, 0)][DBLP ] Conf ] Yun Sik Lee , Peter M. Maurer Two New Techniques for Compiled Multi-Delay Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Larry G. Jones Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Fumiyasu Hirose Performance Evaluation of an Event-Driven Logic Simulation Machine. [Citation Graph (0, 0)][DBLP ] Conf ] D. A. Zein , O. P. Engel , Gary S. Ditlow HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jun Hsu , Wen-Zen Shen Coalgebraic Division for Multilevel Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Kuang-Chien Chen , Masahiro Fujita Efficient Sum-to-One Subsets Algorithm for Logic Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Abdul A. Malik Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Batek , John P. Hayes Test-Set Preserving Logic Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Collet Design and Integration Services (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Albert E. Ruehli , Hansruedi Heeb Challenges and Advances in Electrical Interconnect Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Paul D. Franzon , Slobodan Simovich , Michael Steer , Mark Basel , Sharad Mehrotra , Tom Mills Tools to Aid in Wiring Rule Generation for High Speed Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Norman H. Chang , Keh-Jeng Chang , John Leo , Ken Lee , Soo-Young Oh IPDA: Interconnect Performance Design Assistant. [Citation Graph (0, 0)][DBLP ] Conf ] Wing Ning Li , Andrew Lim , Prathima Agrawal , Sartaj Sahni On the Circuit Implementation Problem. [Citation Graph (0, 0)][DBLP ] Conf ] D. S. Kung , Robert F. Damiano , T. A. Nix , D. J. Geiger BDDMAP: A Technology Mapper Based on a New Covering Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Fishburn LATTIS: An Iterative Speedup Heuristic for Mapped Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal Chaudhary , Massoud Pedram A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Arny Goldfein Why is Today's CAD Inadequate for Designing Tomorrow's Computers (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Margarida F. Jacome , Stephen W. Director Design Process Management for CAD Frameworks. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Beggs , John Sawaya , Catharine Ciric , Julius Etzl Automated Design Decision Support System. [Citation Graph (0, 0)][DBLP ] Conf ] Iksoo Pyo , Ching-Long Su , Ing-Jer Huang , Kuo-Rueih Pan , Yong-Seon Koh , Chi-Ying Tsui , Hsu-Tsun Chen , Gino Cheng , Shihming Liu , Shiqun Wu , Alvin M. Despain Application-Driven Design Automation for Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Hai Chao , Yu-Chin Hsu , Jan-Ming Ho Zero Skew Clock Net Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Mitsuhashi , Ernest S. Kuh Power and Ground Network Topology Optimization for Cell Based VLSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Xianlong Hong , Jin Huang , Chung-Kuan Cheng , Ernest S. Kuh FARM: An Efficient Feed-Through Pin Assignment Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jon Frankle Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Siu-Wing Cheng , Hsi-Chuan Chen , David Hung-Chang Du , Andrew Lim The Role of Long and Short Paths in Circuit Performance Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer , Sharad Malik , Albert Wang Certified Timing Verification and the Transition Delay of a Logic Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Damiani , Giovanni De Micheli Recurrence Equations and the Optimization of Synchronous Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srimat T. Chakradhar , Suman Kanjilal , Vishwani D. Agrawal Finite State Machine Synthesis with Fault Tolerant Test Function. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Lavagno , Cho W. Moon , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Solving the State Assignment Problem for Signal Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Kwang-Ting Cheng State Assignment Using Input/Output Functions. [Citation Graph (0, 0)][DBLP ] Conf ] L. Lanzo Frameworks - User's Perspective (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Chuan Fang , Wu-Shiung Feng , Shian-Lang Lee A New Efficient Approach to Multilayer Channel Routing Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Fujii , Yoko Mima , Tsuneo Matsuda , Takeshi Yoshimura A Multi-Layer Channel Router with New Style of Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Tsung Ho New Models for Four- and Five-Layer Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Cliff Yungchin Hou , C. Y. Roger Chen A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Sivakumar Natarajan , Naveed A. Sherwani , Nancy D. Holmes , Majid Sarrafzadeh Over-the-Cell Channel Routing for High Performance Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Wu , Naveed A. Sherwani , Nancy D. Holmes , Majid Sarrafzadeh Over-the-Cell Routers for New Cell Model. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Te Lai , Sarma Sastry Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati , Fulvio Corno , Silvano Gai , Paolo Prinetto , Matteo Sonza Reorda A New Model for Improving symbolic Product Machine Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Pixley , Seh-Woong Jeong , Gary D. Hachtel Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ray Mercer , Rohit Kapur , Don E. Ross Functional Approaches to Generating Orderings for Efficient Symbolic Representations. [Citation Graph (0, 0)][DBLP ] Conf ] June-Kyung Rho , Fabio Somenzi Inductive Verification of Iterative Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yew-Hong Leong , William P. Birmingham The Automatic Generation of Bus-Interface Models. [Citation Graph (0, 0)][DBLP ] Conf ] Usha Prabhu , Barry M. Pangrle Superpipelined Control and Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Dutta , Jayanta Roy , Ranga Vemuri Distributed Design-Space Exploration for High-Level Synthesis Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ruchir Puri , Jun Gu An Efficient algorithm for Microword Length Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , Donald Lobo , Andreas Kuehlmann Control Optimization in High-Level Synthesis Using Behavioral Don't Cares. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Karri , Alex Orailoglu Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Hilary J. Kahn , Richard Goldman The Electronic Design Interchange Format EDIF: Present and Future. [Citation Graph (0, 0)][DBLP ] Conf ] Todd J. Scallan CAD Framework Initiative - A User Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Ryosuke Okuda , Sumio Oguri An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style. [Citation Graph (0, 0)][DBLP ] Conf ] Youlin Liao , Stan Chow Routing Considerations in Symbolic Layout Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Soohong Kim , Robert Michael Owens , Mary Jane Irwin Experiments with a Performance Driven Module Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Mikael Palczewski Plane Parallel a Maze Router and Its Application to FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Prabir C. Maulik , L. Richard Carley , Rob A. Rutenbar A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Dharchoudhury , Sung-Mo Kang An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Nabors , Jacob White Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Eurich The State of EDA Standards (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Charles A. Shaw Manufacturing Interface (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] 