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Conferences in DBLP

Design Automation Conference (DAC) (dac)
1991 (conf/dac/91)

  1. Catherine H. Gebotys, Mohamed I. Elmasry
    Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:2-7 [Conf]
  2. Shiv Prakash, Alice C. Parker
    Synthesis of Application-Specific Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:8-13 [Conf]
  3. Louis J. Hafer
    Constraint improvements for MILP-based hardware synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:14-19 [Conf]
  4. Yung-Ho Shih, Sung-Mo Kang
    ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:20-25 [Conf]
  5. Alexander D. Stein, Tuyen V. Nguyen, Binay J. George, Ronald A. Rohrer
    ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:26-31 [Conf]
  6. Chandramouli Visweswariah, Ronald A. Rohrer
    Efficient Simulation of Bipolar Digital ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:32-37 [Conf]
  7. Harvey Jones
    Global Stratgies for Electronic Design (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:38- [Conf]
  8. Wayne Wei-Ming Dai, Tal Dayan, David Staepelaere
    Topological Routing in SURF: Generating a Rubber-Band sketch. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:39-44 [Conf]
  9. Wayne Wei-Ming Dai, Raymond Kong, Masao Sato
    Routability of a Rubber-Band Sketch. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:45-48 [Conf]
  10. Deborah C. Wang
    Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:49-53 [Conf]
  11. Manuela Raith, Marc Bartholomeus
    A New Hypergraph Based Rip-Up and Reroute Strategy. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:54-59 [Conf]
  12. Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen
    Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:60-65 [Conf]
  13. Andrzej Krasniewski
    Logic Synthesis for Efficient Pseudoexhaustive Testability. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:66-72 [Conf]
  14. Weiwei Mao, Michael D. Ciletti
    Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:73-79 [Conf]
  15. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:80-86 [Conf]
  16. Thomas W. Williams, Bill Underwood, M. Ray Mercer
    The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:87-92 [Conf]
  17. M. Crastes, K. Sakouti, Gabriele Saucier
    A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:93-98 [Conf]
  18. Massoud Pedram, Narasimha B. Bhat
    Layout Driven Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:99-105 [Conf]
  19. Van Morgan, David Gregory
    An ECL Logic Synthesis System. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:106-111 [Conf]
  20. Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh
    Timing Optimization on Mapped Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:112-117 [Conf]
  21. Gennady G. Kazyonnov
    Design Automation in the Soviet Union: History and Status (Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:118- [Conf]
  22. Andrew Rappaport
    Implementing the Vision: Electronic Design in the 1990's (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:119- [Conf]
  23. Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
    Channel Density Reduction by Routing Over The Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:120-125 [Conf]
  24. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:126-131 [Conf]
  25. Richard J. Enbody, Gary Lynn, Kwee Heong Tan
    Routing the 3-D Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:132-137 [Conf]
  26. E. Vandris, Gerald E. Sobelman
    Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:138-143 [Conf]
  27. Vijay Pitchumani, Pankaj Mayor, Nimish Radia
    A System for Fault Diagnosis and Simulation of VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:144-150 [Conf]
  28. Yoshihiro Kitamura
    Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:151-154 [Conf]
  29. Srinivas Patil, Prithviraj Banerjee, Janak H. Patel
    Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:155-159 [Conf]
  30. Pier Luca Montessoro, Silvano Gai
    Creator: General and Efficient Multilevel Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:160-163 [Conf]
  31. Kwang-Ting Cheng
    On Removing Redundancy in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:164-169 [Conf]
  32. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A Framework for Satisfying Input and Output Encoding Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:170-175 [Conf]
  33. Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio
    A Unified Approach to Input-Output Encoding for FSM State Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:176-181 [Conf]
  34. Martin Geiger, Thomas Müller-Wipperfürth
    FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:182-185 [Conf]
  35. Michael C. McFarland
    Intellectual Property (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:186- [Conf]
  36. Dwight D. Hill
    A CAD System for the Design of Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:187-192 [Conf]
  37. Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto
    Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:193-198 [Conf]
  38. Charles R. Yount, Daniel P. Siewiorek
    SIDECAR: Design Support for Reliability. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:199-204 [Conf]
  39. Wing Yee Au, Daniel Weise, Scott Seligman
    Automatic Generation of Compiled Simulations through Program Specialization. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:205-210 [Conf]
  40. Larry G. Jones
    Accelerating Switch-Level Simulation by Function Caching. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:211-214 [Conf]
  41. Marko P. Chew, Andrzej J. Strojwas
    Utilizing Logic Information in Multi-Level Timing Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:215-218 [Conf]
  42. Alok Jain, Randal E. Bryant
    Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:219-222 [Conf]
  43. Jack V. Briner Jr., John L. Ellis, Gershon Kedem
    Breaking the Barrier of Parallel Simulation of Digital Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:223-226 [Conf]
  44. Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
    Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:227-233 [Conf]
  45. Silvia Ercolani, Giovanni De Micheli
    Technology Mapping for Electrically Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:234-239 [Conf]
  46. Kevin Karplus
    Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:240-243 [Conf]
  47. Kevin Karplus
    Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:244-247 [Conf]
  48. Nam Sung Woo
    A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:248-251 [Conf]
  49. Wojciech Maly
    What is Design for Manufacturability (DFM)? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:252- [Conf]
  50. Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima
    Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:253-258 [Conf]
  51. Christian Masson, Remy Escassut, Denis Barbier, Daniel Winer, Gregory Chevallier
    Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:259-264 [Conf]
  52. Krzysztof Kozminski
    Benchmarks for Layout Synthesis - Evolution and Current Status. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:265-270 [Conf]
  53. Scott Chiu, Christos A. Papachristou
    A Design for Testability Scheme with Applications to Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:271-277 [Conf]
  54. Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
    Enhanced Controllability for IDDQ Test Sets Using Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:278-281 [Conf]
  55. Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce
    ATPG Based on a Novel Grid-Addressable Latch Element. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:282-286 [Conf]
  56. Chien-In Henry Chen
    Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:287-290 [Conf]
  57. David M. Wu, Charles E. Radke
    Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:291-295 [Conf]
  58. Kuan-Jen Lin, Chen-Shang Lin
    Automatic Synthesis of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:296-301 [Conf]
  59. Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli
    Algorithms for Synthesis of Hazard-Free Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:302-308 [Conf]
  60. Maureen Ladd, William P. Birmingham
    Synthesis of Multiple-Input Change Asynchronous Finite state Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:309-314 [Conf]
  61. A. Richard Newton
    Framework Standards: How Important are They? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:315- [Conf]
  62. Robert C. Carden IV, Chung-Kuan Cheng
    A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:316-321 [Conf]
  63. Andrew B. Kahng, Jason Cong, Gabriel Robins
    High-Performance Clock Routing Based on Recursive Geometric Aatching. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:322-327 [Conf]
  64. Yang Cai, D. F. Wong
    On Minimizing the Number of L-Shaped Channels. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:328-334 [Conf]
  65. Mohankumar Guruswamy, D. F. Wong
    A General Multi-Layer Area Router. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:335-340 [Conf]
  66. Irith Pomeranz, Sudhakar M. Reddy
    On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:341-346 [Conf]
  67. Stephen Pateras, Janusz Rajski
    Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:347-352 [Conf]
  68. Srimat T. Chakradhar, Vishwani D. Agrawal
    A Transitive Closure Based Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:353-358 [Conf]
  69. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:359-365 [Conf]
  70. David C. Ku, Dave Filo, Giovanni De Micheli
    Control Optimization Based on Resynchronization of Operations. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:366-371 [Conf]
  71. Bernhard Eschermann, Hans-Joachim Wunderlich
    A Unified Approach for the Synthesis of Self-Testable Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:372-377 [Conf]
  72. Christos A. Papachristou, Scott Chiu, Haidar Harmanani
    A Data Path Synthesis Method for Self-Testable Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:378-384 [Conf]
  73. Vijay Raghavendra, Chidchanok Lursinsap
    Automated Micro-Roll-back Self-Recovery Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:385-390 [Conf]
  74. Holger Busch, Gerd Venzl
    Proof-Aided Design of Verified Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:391-396 [Conf]
  75. Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger
    Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:397-402 [Conf]
  76. Jerry R. Burch, Edmund M. Clarke, David E. Long
    Representing Circuits More Efficiently in Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:403-407 [Conf]
  77. Jerry R. Burch
    Using BDDs to Verify Multipliers. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:408-412 [Conf]
  78. Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima
    Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:413-416 [Conf]
  79. Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
    Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:417-420 [Conf]
  80. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    A General Purpose Multiple Way Partitioning Algorithm. [Citation Graph (2, 0)][DBLP]
    DAC, 1991, pp:421-426 [Conf]
  81. Georg Sigl, Konrad Doll, Frank M. Johannes
    Analytical Placement: A Linear or a Quadratic Objective Function? [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:427-432 [Conf]
  82. Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
    Branch-and-Bound Placement for Building Block Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:433-439 [Conf]
  83. Wen Ching Wu, Chung-Len Lee
    A Probabilistic Testability Measure for Delay Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:440-445 [Conf]
  84. Peter A. Beerel, Teresa H. Y. Meng
    Testability of Asynchronous Timed Control Circuits with Delay Assumptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:446-451 [Conf]
  85. Sarma Sastry, Amitava Majumdar
    A Branching Process Model for Observability Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:452-457 [Conf]
  86. Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
    A Resynthesis Approach for Network Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:458-463 [Conf]
  87. Johnson Chan Limqueco, Saburo Muroga
    Logic Optimization of MOS Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:464-469 [Conf]
  88. Søren Søe, Kevin Karplus
    Logic Minimization using Two-column Rectangle Replacement. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:470-473 [Conf]
  89. Gerd Venzl
    Are Formal Methods in Design for Real? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:474- [Conf]
  90. King C. Ho, Sarma Sastry
    Flexible Transistor Matrix (FTM). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:475-480 [Conf]
  91. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:481-486 [Conf]
  92. Robert L. Maziasz, John P. Hayes
    Exact Width and Height Minimization of CMOS Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:487-493 [Conf]
  93. Scott D. Huss, Ronald S. Gyurcsik
    Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:494-499 [Conf]
  94. George Gad-El-Karim, Ronald S. Gyurcsik
    Generation of Performance Sensitivities for Analog Cell Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:500-505 [Conf]
  95. Louis-Oliver Donzelle, Pierre-François Dubois, B. Hennion, J. Parissis, P. Senn
    A Constraint Based Approach to Automatic Design of Analog Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:506-509 [Conf]
  96. Masato Mogaki, Naoki Kato, Naomi Shimada, Yuriko Yamada
    A Layout Improvement Method Based on Constraint Propagation for Analog LSI's. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:510-513 [Conf]
  97. Kayhan Küçükçakar, Alice C. Parker
    CHOP: A Constraint-Driven System-Level Partitioner. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:514-519 [Conf]
  98. Thomas E. Fuhrman
    Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:520-525 [Conf]
  99. Nikil D. Dutt, James R. Kipps
    Bridging High-Level Synthesis to RTL Technology Libraries. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:526-529 [Conf]
  100. Alice C. Parker, Pravil Gupta, Agha Hussain
    The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:530-534 [Conf]
  101. Li-Ren Liu, David Hung-Chang Du, Hsi-Chuan Chen
    An Efficient Parallel Critical Path Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:535-540 [Conf]
  102. Yun-Cheng Ju, Resve A. Saleh
    Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:541-546 [Conf]
  103. Hsi-Chuan Chen, David Hung-Chang Du, Li-Ren Liu
    Critical Path Selection for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:547-550 [Conf]
  104. Jengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen
    Timing Verification on a 1.2M-Device Full-Custom CMOS Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:551-554 [Conf]
  105. Curtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage
    RICE: Rapid Interconnect Circuit Evaluator. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:555-560 [Conf]
  106. Vivek Raghavan, Ronald A. Rohrer
    A New Nonlinear Driver Model for Interconnect Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:561-566 [Conf]
  107. Heinz Mattes, Wolfgang Weisenseel, Gerhard Bischof, Reimund Dachauer
    Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:567-572 [Conf]
  108. Goodwin R. Chin, Walter C. Dietrich Jr., Duane S. Boning, Alexander S. Wong, Andrew R. Neureuther, Robert W. Dutton
    Linking TCAD to EDA - Benefits and Issues. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:573-578 [Conf]
  109. D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas
    A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:579-584 [Conf]
  110. Lifeng Wu, Zhilian Yang, Zhiping Yu, Zhijian Li
    GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:585-590 [Conf]
  111. Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
    Data-Path Synthesis Using Path Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:591-596 [Conf]
  112. Stefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man
    Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:597-602 [Conf]
  113. C. Y. Roger Chen, Michael Z. Moricz
    Datapath Scheduling for Two-Level Pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:603-606 [Conf]
  114. Barry M. Pangrle, Forrest Brewer, Donald Lobo, Andrew Seawright
    Relevant Issues in High-Level Connectivity Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:607-610 [Conf]
  115. Alberto L. Sangiovanni-Vincentelli
    Testability Solutions: Who Really Wants Them? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:611- [Conf]
  116. Jacques Benkoski, Andrzej J. Strojwas
    The Role of Timing Verification in Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:612-619 [Conf]
  117. Ren-Song Tsay, Jürgen Koehl
    An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:620-625 [Conf]
  118. Wing K. Luk
    A Fast Physical Constraint Generator for Timing Driven Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:626-631 [Conf]
  119. Suphachai Sutanthavibul, Eugene Shragowitz
    Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:632-635 [Conf]
  120. Arvind Srinivasan
    An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:636-639 [Conf]
  121. Donald A. Joy, Maciej J. Ciesielski
    Placement for Clock Period Minimization With Multiple Wave Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:640-643 [Conf]
  122. Farid N. Najm
    Transition Density, A Stochastic Measure of Activity in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:644-649 [Conf]
  123. Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima
    Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:650-655 [Conf]
  124. Tod Amon, Gaetano Borriello
    OEsim: A Simulator for Timing Behavior. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:656-661 [Conf]
  125. Dimitris Doukas, Andrea S. LaPaugh
    CLOVER: A Timing Constraints Verification System. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:662-667 [Conf]
  126. Jen-Pin Weng, Alice C. Parker
    3D Scheduling: High-Level Synthesis with Floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:668-673 [Conf]
  127. Tai A. Ly, Jack T. Mowchenko
    Bottom Up Synthesis Based on Fuzzy Schedules. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:674-679 [Conf]
  128. In-Cheol Park, Chong-Min Kyung
    Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:680-685 [Conf]
  129. Rajiv Jain, Ashutosh Mujumdar, Alok Sharma, Hueymin Wang
    Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:686-689 [Conf]
  130. Tod Amon, Gaetano Borriello
    Sizing Synchronization Queues: A Case Study in Higher Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:690-693 [Conf]
  131. Wayne Allen, Douglas Rosenthal, Kenneth W. Fiduk
    The MCC CAD Framework Methodology Management System. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:694-698 [Conf]
  132. Steve Banks, Catherine Bunting, Russ Edwards, Laura Fleming, Peter Hackett
    A Configuration Management System in a Data Management Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:699-703 [Conf]
  133. Flávio Rech Wagner, Arnaldo Hilário Viegas de Lima
    Design Version Management in the GARDEN Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:704-710 [Conf]
  134. K. Olav ten Bosch, Peter Bingley, Pieter van der Wolf
    Design Flow Management in the NELSIS CAD Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:711-716 [Conf]
  135. Jerry P. Hwang
    REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:717-722 [Conf]
  136. Matthias C. Utesch
    A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:723-726 [Conf]
  137. Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya
    A Two-Dimensional Topological Compactor With Octagonal Geometry. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:727-731 [Conf]
  138. Andrew J. Harrison
    VLSI Layout Compaction Using Radix Priority Search Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:732-735 [Conf]
  139. Debaprosad Dutt, Chi-Yuan Lo
    On Minimal Closure Constraint Generation for Symbolic Cell Assembly. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:736-739 [Conf]
  140. Jaijeet S. Roychowdhury, Donald O. Pederson
    Efficient Transient Simulation of Lossy Interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:740-745 [Conf]
  141. J. S. Barkatullah, S. Chowdhury
    A Transmission Line Simulator for GaAs Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:746-751 [Conf]
  142. Andrew T. Yang, C. H. Chan, Jack T. Yao, R. R. Daniels, J. P. Harrang
    Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:752-757 [Conf]
  143. Xiaobo Hu, Ronald G. Harber, Steven C. Bass
    Minimizing the Number of Delay Buffers in the Synchronization of Pipelined Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:758-763 [Conf]
  144. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    Scheduling for Functional Pipelining and Loop Winding. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:764-769 [Conf]
  145. Alexandru Nicolau, Roni Potasman
    Incremental Tree Height Reduction for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:770-774 [Conf]
  146. Donald Lobo, Barry M. Pangrle
    Redundant Operator Creation: A Scheduling Optimization Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:775-778 [Conf]
  147. Jonathan Rose
    Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:779- [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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